ARM720T™ Technical Reference Manual 9.25. Debug status register

9.25. Debug status register

The debug status register is 13 bits wide. If it is accessed for a write (with the read/write bit set), the status bits are written. If it is accessed for a read (with the read/write bit clear), the status bits are read. The format of the debug status register is shown in Figure 9.16.

Figure 9.16. Debug status register format

The function of each bit in this register is shown in Table 9.11.

Table 9.11. Debug status register bit assignments

Bit	Function
12	Enables the debugger to determine whether the core has entered debug state due to the assertion of DBGRQ.
4	Enables TBIT to be read. This enables the debugger to determine what state the processor is in, and which instructions to execute.
3	Enables the state of the HTRANS[1] signal from the core to be read. This enables the debugger to determine whether a memory access from the debug state has completed.
2	Enables the state of the core interrupt enable signal, IFEN, to be read.
1	Enables the values on the synchronized version of DBGRQ to be read.
0	Enables the values on the synchronized versions of DBGACK to be read.

The structure of the debug control and status registers is shown in Figure 9.17.

Figure 9.17. Debug control and status register structure

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