3.3.10. Dynamic Memory Write Recovery Time
Register, MPMCDynamictWR
The four-bit, read/write, MPMCDynamictWR Register enables
you to program the write recovery time, tWR.
It is recommended that this register is modified during system initialization,
or when there are no current or outstanding transactions. This can
be ensured by waiting until the PrimeCell MPMC is idle, and then
entering low-power or disabled mode. This value is normally found
in SDRAM data sheets as tWR, tDPL,
tRWL, or tRDL. This
register can be accessed with one wait state.
Note
This register is used for all four dynamic memory chip selects.
Therefore the worse case value for all of the chip selects must
be programmed.
Table 3.13 lists
the bit assignments for the MPMCDynamictWR Register.
Table 3.13. MPMCDynamictWR Register bit assignments
| Bits | Name | Description |
|---|
| [31:4] | - | Reserved, read undefined, do not modify. |
| [3:0] | tWR | Write recovery time: 0x0-0xE =
n+1 clock cycles
0xF = 16 clock cycles
(reset value on nPOR).
|
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