PrimeCell™ MultiPort Memory Controller (PL175) Technical Reference Manual 3.3.1. Control Register, MPMCControl

3.3.1. Control Register, MPMCControl

The MPMCControl Register is a two-bit, read/write register that controls the memory controller operation. The register fields can only be altered in idle state. This register can be accessed with zero wait states. Table 3.2 lists the bit assignments for the MPMCControl Register.

Table 3.2. MPMCControl Register bit assignments

Bits	Name	Description
[31:3]	-	Reserved, read undefined, do not modify.
[2]	L	Low-power mode, indicates normal or low-power mode: 0 = normal mode (reset value on nPOR and HRESETn) 1 = low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by AHB, or power-on reset. You must only modify this bit when the MPMC is in idle state.^[1]^[2]
[1]	-	Reserved, read undefined, do not modify
[0]	E	MPMC enable, indicates if the PrimeCell MPMC is enabled or disabled: 0 = disabled 1 = enabled (reset value on nPOR and HRESETn). Disabling the PrimeCell MPMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by AHB, or power-on reset. You must only modify this bit when the MPMC is in idle state.^[1]^[2]
^[1]The external memory cannot be accessed in low-power states. If a memory access is performed an error response is generated. ^[2]The memory controller AHB register programming port can be accessed normally. The PrimeCell MPMC registers can be programmed in low-power, and, or disabled state.

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