PrimeCell™ MultiPort Memory Controller (PL175) Technical Reference Manual 3.3.31. Peripheral Identification Registers 0-3, MPMCPeriphID0-3

3.3.31. Peripheral Identification Registers 0-3, MPMCPeriphID0-3

The MPMCPeriphID0-3 Registers are four eight-bit read-only registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single register that holds a 32-bit peripheral ID value.

Table 3.38 lists the bit assignments for the conceptual 32-bit MPMC Peripheral Identification Register.

Table 3.38. Conceptual MPMC Peripheral Identification Register bit assignments

Bits	Name	Description
[31:24]	Configuration	Configuration options are peripheral-specific. See Peripheral Identification Register 3, MPMCPeriphID3 register.
[23:20]	Revision	The peripheral revision number.
[19:12]	Designer	Designer’s ID number. This is `0x41` for ARM.
[11:0]	Part number	Identifies the peripheral. The part number for PL175 is `0x175`.

Figure 3.1 shows the correspondence between bits of the MPMCPeriphID0-3 registers and the conceptual 32-bit MPMC Peripheral ID register.

Figure 3.1. Peripheral Identification Register bit assignments

The four eight-bit peripheral identification registers are described in the following subsections:

Peripheral Identification Register 0, MPMCPeriphID0

The MPMCPeriphID0 Register is hard-coded and the fields within the register determine the reset value. Table 3.39 lists the bit assignments for the MPMCPeriphID0 Register.

Table 3.39. MPMCPeriphID0 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined
[7:0]	PartNumber0	These bits read back as `0x75`

Peripheral Identification Register 1, MPMCPeriphID1 register

The MPMCPeriphID1 Register is hard-coded and the fields within the register determine the reset value. Table 3.40 lists the bit assignments for the MPMCPeriphID1 Register.

Table 3.40. MPMCPeriphID1 Register bit assignments

Bits	Name	Type	Description
[31:8]	-	-	Reserved, read undefined
[7:4]	Designer0	Read	These bits read back as `0x1`
[3:0]	PartNumber1	Read	These bits read back as `0x1`

Peripheral Identification Register 2, MPMCPeriphID2 register

The MPMCPeriphID2 Register is hard-coded and the fields within the register determine the reset value. Table 3.41 lists the bit assignments for the MPMCPeriphID2 Register.

Table 3.41. MPMCPeriphID2 Register bit assignments

Bits

Name

Type

Bits	Name	Type	Description
[31:8]	-	-	Reserved, read undefined.
[7:4]	Revision	Read	These bits read back as the revision number. `0x0` = PL175 revision r1p0 `0x0` = PL175 revision r1p1 `0x0` = PL175 revision r1p2 `0x0` = PL175 revision r1p3.
[3:0]	Designer1	Read	These bits read back as `0x4`.

Description

[31:8]

Reserved, read undefined.

[7:4]

Revision

Read

These bits read back as the revision number.

0x0 = PL175 revision r1p0

0x0 = PL175 revision r1p1

0x0 = PL175 revision r1p2

0x0 = PL175 revision r1p3.

[3:0]

Designer1

Read

These bits read back as 0x4.

Peripheral Identification Register 3, MPMCPeriphID3 register

The MPMCPeriphID3 register is hard-coded and the fields within the register determine the reset value. Table 3.42 lists the bit assignments for the MPMCPeriphID3 register.

Table 3.42. MPMCPeriphID3 Register bit assignments

Bits	Name	Type	Description
[31:6]	-	-	Reserved, read undefined.
[5:3]	Configuration	Read	Indicates the AHB master bus width: b000 = 32-bit wide b001 = 64-bit wide b010 = 128-bit wide b011 = 256-bit wide b100 = 512-bit wide b101 = 1024-bit wide b110-b111 = reserved For PL175 this field is set to b000.
[2]	Configuration	Read	TIC interface: 0 = no 1 = yes For PL175 this field is set to 1.
[1]	Configuration	Read	Data buffers: 0 = no 1 = yes For PL175 this field is set to 1.
[0]	Configuration	Read	Static memory controller: 0 = no 1 = yes For PL175 this field is set to 1.

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