PrimeCell ™ MultiPortMemory Controller (PL175) Technical Reference Manual


Table of Contents

About this document
Product revision status
Intended audience
Using this manual
Further reading
Feedback on this product
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1. Introduction
1.1. About the ARM PrimeCell MPMC (PL175)
1.1.1. Features of the PrimeCell MPMC
1.2. Supported dynamic memory devices
1.2.1. Examples of JEDEC DDR-SDRAM devices
1.2.2. Examples of JEDEC SDRAM devices
1.2.3. Examples of Micron style SyncFlashdevices
1.2.4. Examples of JEDEC low-power SDRAMdevices
1.3. Supported static memory devices
1.3.1. Examples of ROM devices
1.3.2. Examples of page mode ROM devices
1.3.3. Examples of SRAM devices
1.3.4. Examples of flash devices
1.3.5. Examples of page mode flash devices
1.4. Product revisions
2. Functional Overview
2.1. PrimeCell MPMC functional description
2.1.1. AHB slave register interface
2.1.2. AHB slave memory interfaces
2.1.3. Data buffers
2.1.4. Arbiter
2.1.5. Memory controller state machine
2.1.6. Pad interface
2.1.7. Test Interface Controller (TIC)
2.1.8. EBI
2.2. Overview of a PrimeCell MPMC, ASIC,or ASSP system
2.2.1. External bus
2.2.2. Internal bus
2.3. Low-power operation
2.3.1. Low-power SDRAM deep sleep mode
2.3.2. Low-power SDRAM partial array refresh
2.4. Lock and semaphores
2.5. Burst types
2.6. Busy transfer type
2.7. Arbitration
2.7.1. Re-arbitration occurrence
2.7.2. Re-arbitration priority
2.7.3. AHB memory port latency
2.8. Worst case transaction latency
2.8.1. Worst case transaction latency forthe highest priority AHB memory port
2.8.2. Worst case transaction latency forthe lower priority AHB memory ports
2.8.3. System factors affecting worst caselatency
2.9. Sharing memory bandwidth between AHBports
2.9.1. Typical AHB port TimeOut value givenbandwidth requirement
2.9.2. Typical AHB port TimeOut value givenpercentage of memory bandwidth requirement
2.9.3. Typical AHB bandwidth requirement example
2.9.4. Typical AHB percentage bandwidth example
2.10. Memory bank select
2.11. Memory map
2.11.1. Chip select 1 static memory configuration
2.11.2. Chip select 5 SDRAM memory configuration
2.11.3. Boot from flash, SRAM remapped after boot
2.11.4. Example of a boot from flash, SDRAM remapped afterboot
2.11.5. Memory aliasing
2.11.6. Unused AHB HADDRx address bits
2.12. Sharing memory interface signals
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. Control Register, MPMCControl
3.3.2. Status Register, MPMCStatus
3.3.3. Configuration Register, MPMCConfig
3.3.4. Dynamic Memory Control Register, MPMCDynamicControl
3.3.5. Dynamic Memory RefreshTimer Register, MPMCDynamicRefresh
3.3.6. Dynamic Memory ReadConfiguration Register, MPMCDynamicReadConfig
3.3.7. Dynamic Memory PrechargeCommand Period Register, MPMCDynamictRP
3.3.8. Dynamic Memory Active To PrechargeCommand Period Register, MPMCDynamictRAS
3.3.9. Dynamic Memory Self-refreshExit Time Register, MPMCDynamictSREX
3.3.10. Dynamic Memory Write Recovery TimeRegister, MPMCDynamictWR
3.3.11. Dynamic Memory Active To Active CommandPeriod Register, MPMCDynamictRC
3.3.12. Dynamic Memory Auto-refreshPeriod Register, MPMCDynamictRFC
3.3.13. Dynamic Memory ExitSelf-refresh Register, MPMCDynamictXSR
3.3.14. Dynamic Memory Active Bank A To ActiveBank B Time Register, MPMCDynamictRRD
3.3.15. Dynamic Memory Load Mode Register,MPMCDynamictMRD
3.3.16. Dynamic Memory LastData In To Read Command Time Register, MPMCDynamictCDLR
3.3.17. Static Memory Extended Wait Register,MPMCStaticExtendedWait
3.3.18. Dynamic Memory Configuration Registers0-3, MPMCDynamicConfig0-3
3.3.19. Dynamic Memory RAS and CAS Delay Registers0-3, MPMCDynamicRasCas0-3
3.3.20. Static Memory Configuration Registers0-3, MPMCStaticConfig0-3
3.3.21. Static Memory WriteEnable Delay Registers 0-3, MPMCStaticWaitWen0-3
3.3.22. Static Memory Output Enable DelayRegisters 0-3, MPMCStaticWaitOen0-3
3.3.23. Static Memory Read Delay Registers0-3, MPMCStaticWaitRd0-3
3.3.24. Static Memory Page Mode Read DelayRegisters 0-3, MPMCStaticWaitPage0-3
3.3.25. Static Memory Write Delay Registers0-3, MPMCStaticWaitWr0-3
3.3.26. Static Memory Turn Round Delay Registers0-3, MPMCStaticWaitTurn0-3
3.3.27. AHB Control Registers 0-5, MPMCAHBControl0-5
3.3.28. AHB Status Registers0-5, MPMCAHBStatus0-5
3.3.29. AHB TimeOut Registers 0-5, MPMCAHBTimeOut0-5
3.3.30. Additional Peripheral IdentificationRegisters 4-7, MPMCPeriphID4-7
3.3.31. Peripheral Identification Registers0-3, MPMCPeriphID0-3
3.3.32. PrimeCell IdentificationRegisters 0-3, MPMCPCellID0-3
4. Programmer’s Model for Test
4.1. PrimeCell MPMC test harness overview
4.1.1. AMBA test strategy
4.1.2. Non-AMBA intra-chip integration test strategy
4.1.3. Primary I/O test strategy
4.2. Production test
4.3. Test registers
4.3.1. Test Control Register, MPMCITCR
4.3.2. Test Input 0 Register,MPMCITIP0
4.3.3. Test Input 1 Register, MPMCITIP1
4.3.4. Test Output Register, MPMCITOP
A. Signal Descriptions
A.1. AHB register signals
A.2. AHB memory signals
A.3. Miscellaneous signals
A.3.1. Miscellaneous signals
A.3.2. Tie-off signals
A.3.3. Test signals
A.3.4. Clock signals
A.3.5. External Bus Interface signals
A.4. Pad interface and control signals
A.4.1. Signal descriptions
A.4.2. Values during resetand self-refresh
A.5. Test Interface Controller (TIC) AHBsignals
A.6. Scan test signals

List of Tables

2.1. Read buffer enabled
2.2. Read buffer disabled
2.3. Read buffer enabled
2.4. Read buffer disabled
2.5. Write buffer enabled
2.6. Write buffer disabled
2.7. Write buffer enabled
2.8. Write buffer disabled
2.9. Memory bank selection
3.1. PrimeCell MPMC register summary
3.2. MPMCControl Register bit assignments
3.3. MPMCStatus Register bit assignments
3.4. MPMCConfig Register bit assignments
3.5. MPMCDynamicControl Register bit assignments
3.6. Clock status options
3.7. Output voltage settings
3.8. MPMCDynamicRefresh Register bit assignments
3.9. MPMCDynamicReadConfig Register bit assignments
3.10. MPMCDynamictRP Register bit assignments
3.11. MPMCDynamictRAS Register bit assignments
3.12. MPMCDynamictSREX Register bit assignments
3.13. MPMCDynamictWR Register bit assignments
3.14. MPMCDynamictRC Register bit assignments
3.15. MPMCDynamictRFC Register bit assignments
3.16. MPMCDynamictXSR Register bit assignments
3.17. MPMCDynamictRRD Register bit assignments
3.18. MPMCDynamictMRD Register bit assignments
3.19. MPMCDynamictCDLR Register bit assignments
3.20. MPMCStaticExtendedWait Register bit assignments
3.21. MPMCDynamicConfig0-3 Register bit assignments
3.22. Address mapping
3.23. MPMCDynamicRasCas0-3 Register bit assignments
3.24. MPMCStaticConfig0-3 Register bit assignments
3.25. MPMCStaticWaitWen0-3 Register bit assignments
3.26. MPMCStaticWaitOen0-3 Register bit assignments
3.27. MPMCStaticWaitRd0-3 Register bit assignments
3.28. MPMCStaticWaitPage0-3 Register bit assignments
3.29. MPMCStaticWaitWr0-3 Register bit assignments
3.30. MPMCStaticWaitTurn0-3 Register bit assignments
3.31. MPMCAHBControl0-5 Register bit assignments
3.32. Transfer types
3.33. MPMCAHBStatus0-5 Register bit assignments
3.34. MPMCAHBTimeOut0-5 Register bit assignments
3.35. Conceptual MPMC Additional Peripheral ID Register bit assignments
3.36. MPMCPeriphID4 Register bit assignments
3.37. MPMCPeriphID5-7 Register bit assignments
3.38. Conceptual MPMC Peripheral Identification Register bit assignments
3.39. MPMCPeriphID0 Register bit assignments
3.40. MPMCPeriphID1 Register bit assignments
3.41. MPMCPeriphID2 Register bit assignments
3.42. MPMCPeriphID3 Register bit assignments
3.43. Conceptual PrimeCell ID Register bit assignments
4.1. Test registers memory map
4.2. MPMCITCR Register bit assignments
4.3. MPMCITIP0 Register bit assignments
4.4. MPMCITIP1 Register bit assignments
4.5. MPMCITOP Register bit assignments
A.1. AHB register signal descriptions
A.2. AHB memory signal descriptions
A.3. Miscellaneous signals
A.4. Tie-off signal descriptions
A.5. Test signal descriptions
A.6. Clock signal descriptions
A.7. EBI signal descriptions
A.8. Pad interface and control signal descriptions
A.9. Pad interface and control signal values during reset andself-refresh
A.10. TIC signal descriptions
A.11. Scan test signal descriptions


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A July2002 First release.
Revision B 19February 2003 Updated for r1p1.
Revision C 23April 2003 Updated for r1p2.
Revision D 8November 2005 Updated for r1p3. Corrected PB bitinformation for reads, in Table 3-24 on page 3-31.Table 3-11on page 3-19 and Table 3-23 on page 3-30 updated for tRAS >RAS requirement.
Copyright © 2002-2003, 2005 ARM Limited. All rights reserved. ARM DDI 0230D