2.2.1. JTAG access

All registers in the ETM are programmed using a JTAG interface. The interface is an extension of the ARM TAP controller, and is assigned scan chain number 6. The scan chain consists of a 40-bit shift register comprising:

All registers in the ETM can be configured using the JTAG interface. The general arrangement of the ETM JTAG registers is shown in Figure 2.2.

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored.

Figure 2.2. ETM JTAG structure

Note

A read or write takes place when the TAP controller enters the UPDATE-DR state.

Restricting JTAG access

JTAG access to the ETM registers can be made read-only by setting bit 22 of the ETM control register, 0x00. This bit can only be set from the coprocessor interface.

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