2.2.2. Coprocessor access

ETM11RV uses ETMv3.1, which provides improved coprocessor access. This enables you to use the ETM as an extended breakpoint unit to test for unit failure while testing multiple devices. The improved coprocessor access also means that you do not have to program each device individually by connecting a probe. You can now do the following without external hardware:

This section describes the changes to the programmer’s model:

Coprocessor model

The software access method is processor-architecture defined. If you are using a non-ARM architecture then you must specify your own method for software access.

All registers of the ETM are mapped to coprocessor 14. All instructions in this coprocessor with Opcode1 equal to 1 are reserved for ETM use.

The instructions to read and write ETM registers are as follows:

MRC p14, 1, Rd, 0, reg[3:0], reg[6:4]
MCR p14, 1, Rd, 0, reg[3:0], reg[6:4]

These instructions have CRn equal to 0 and the register number encoded in Opcode2 and CRm.

Unlike coprocessor accesses to debug registers, a read from a non-existent register returns an Unpredictable value, and a write to a non-existent register silently fails. No Undefined Instruction exceptions are ever generated. It is up to the tools to determine what registers are valid from the programmers' model.

The read-only, write-only, and read/write status of the registers is the same as for JTAG access.

Restricting coprocessor access

Coprocessor access to the ETM registers can be made read-only by setting bit 23 of the ETM control register, 0x00. This bit can only be set from the JTAG interface.

Concurrent access

Concurrent access from the JTAG and coprocessor interfaces is permitted. Conflicting JTAG accesses are delayed by a cycle.

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