3.7. Interaction with the performance monitoring unit

ARM1136JF-S and ARM1136J-S processors include a performance monitoring unit that enables events, such as cache misses and instructions executed, to be counted over a period of time. These events are all available for use by ETM11RV using the extended external input facility. Each bit in the EVNTBUS[19:0] input is mapped to the corresponding extended external input. See the ARM1136JF-S and ARM1136J-S Technical Reference Manual for details of the mapping of events to bits within this bus.

Some events use two bits. Two of these events can occur in a cycle. They must be dealt with separately if they are to be properly counted.

The ARM1136JF-S or ARM1136J-S performance monitoring unit can count the two ETM11RV external outputs as additional events. These events are not provided back to ETM11RV as extended external inputs.These facilities allow the system events to be further qualified with ETM resources, such as instruction address ranges or the start/stop resource, before being passed back to the performance monitoring unit for counting. This can be done as follows:

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