3.8. Reset behavior

The ETM Control Register, 0x00, is reset only on a power-on reset, nPORESET LOW.

The TAP ID register and scan chain select register, updated by the SCAN_N TAP instruction, are reset by driving DBGnTRST LOW or by taking the TAP state machine through the Test-Logic-Reset state.

Copyright © 2002-2003 ARM Limited. All rights reserved.ARM DDI 0233B
Non-Confidential