B.3. Trace interface signals

Table B.1 shows the trace interface timing parameters.

Table B.1. Trace interface timing parameters

Symbol

Parameter

Min

Max

TisetmiactlETMIACTL input set up to rising CLK40%-
TihetmiactlETMIACTL input hold from rising CLK0%-
TisetmiaETMIA input set up to rising CLK40%-
TihetmiaETMIA input hold from rising CLK0%-
TisetmdactlETMDACTL input set up to rising CLK40%-
TihetmdactlETMDACTL input hold from rising CLK0%-
TisetmdaETMDA input set up to rising CLK40%-
TihetmdaETMDA input hold from rising CLK0%-
TisetmddETMDD input set up to rising CLK40%-
TihetmddETMDD input hold from rising CLK0%-
TisetmddctlETMDDCTL input set up to rising CLK40%-
TihetmddctlETMDDCTL input hold from rising CLK0%-
TisetmpadvETMPADV input set up to rising CLK40%-
TihetmpadvETMPADV input hold from rising CLK0%-

Figure B.1 shows the trace interface timing parameters.

Figure B.1. Trace interface timing parameters

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