ETM11RV™ Technical Reference Manual B.3. Trace interface signals

ETM11RV™ Technical Reference Manual

Revision: r0p1

Home > AC Parameters > Trace interface signals

B.3. Trace interface signals

Table B.1 shows the trace interface timing parameters.

Table B.1. Trace interface timing parameters

Symbol	Parameter	Min	Max
T_isetmiactl	ETMIACTL input set up to rising CLK	40%	-
T_ihetmiactl	ETMIACTL input hold from rising CLK	0%	-
T_isetmia	ETMIA input set up to rising CLK	40%	-
T_ihetmia	ETMIA input hold from rising CLK	0%	-
T_isetmdactl	ETMDACTL input set up to rising CLK	40%	-
T_ihetmdactl	ETMDACTL input hold from rising CLK	0%	-
T_isetmda	ETMDA input set up to rising CLK	40%	-
T_ihetmda	ETMDA input hold from rising CLK	0%	-
T_isetmdd	ETMDD input set up to rising CLK	40%	-
T_ihetmdd	ETMDD input hold from rising CLK	0%	-
T_isetmddctl	ETMDDCTL input set up to rising CLK	40%	-
T_ihetmddctl	ETMDDCTL input hold from rising CLK	0%	-
T_isetmpadv	ETMPADV input set up to rising CLK	40%	-
T_ihetmpadv	ETMPADV input hold from rising CLK	0%	-

Figure B.1 shows the trace interface timing parameters.

Figure B.1. Trace interface timing parameters

Copyright © 2002-2003 ARM Limited. All rights reserved.	ARM DDI 0233B
Non-Confidential
PDF version

Home > AC Parameters > Trace interface signals