3.5. Independent load/store unit

ARM1136JF-S and ARM1136J-S cores have independent load/store units. This means that they are capable of continuing to transfer data values for an earlier instruction after later instructions have been executed. In these circumstances, the later instructions are said to have executed underneath the data instruction. When a data instruction has been traced, all instructions executed underneath it are also traced.


This does not create much additional trace, because the instructions executed underneath cannot be data instructions or indirect branches.

All address comparators have a sticky bit that is observed when the comparator is used as shown in Table 3.4.

Table 3.4. Conditions for observing address comparator sticky bits

Comparator usageSingle address comparatorAddress range comparator
Selected as an eventSticky bit ignored Sticky bit observed
Selected by TraceEnableSticky bit ignored Sticky bit ignored
Selected by start/stop blockSticky bit ignored Sticky bit ignored
Selected by ViewDataSticky bit observed Sticky bit observed

Where it is observed, the sticky bit behaves as follows:

Sticky bit set

When the comparator matches the instruction address of a data instruction.

Sticky bit cleared

When the data instruction completes.

The sticky bit is never set for address comparators configured for data addresses.

Where observed, the comparator continues to match while the sticky bit is set.

Single address comparators cannot observe the sticky bit when selected as an event, because they are defined to be active for only one cycle for the benefit of the counters and sequencer. If an event of the kind instruction address = X AND data address = Y is required, the instruction address comparator must be an address range comparator to guarantee that it still matches when the data address comparator matches.

ViewData always observes the sticky bits so that if an instruction address comparator is selected, all the data corresponding to that instruction match. In normal circumstances, you must not use single instruction address comparators as the enabling event, because they do not observe the sticky bit.

There is no requirement for TraceEnable or the start/stop block to observe the sticky bit, because when a data instruction has been traced, tracing cannot be disabled until all data transfers corresponding to that instruction have occurred.


Using data values to create an event, such as a sequencer transition, might result in out-of-order events occurring because the load data might be returned out of order. If you are concerned that the ARM1136JF-S or ARM1136J-S nonblocking cache might affect programmed events, you can disable it in the core by writing to bit 21 of the cp15 Control Register (r1). See the ARM1136JF-S and ARM1136J-S Technical Reference Manual for more information.

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