2.1. About the programmer’s model

When programming the ETM registers you must enable all the changes at the same time. For example, if the counter is reprogrammed, it might start to count based on incorrect events, before the trigger condition has been correctly set up. In addition, the JTAG clock, TCLK, can often be asynchronous to the core clock.

You can use the ETM programming bit in the ETM Control Register to disable all operations during programming. To do this follow the procedure shown in Figure 2.1.

The individual registers are not described here. For more information, see the ETM Architecture Specification.

Figure 2.1. Programming ETM registers

It is not necessary for the core to be in debug state while the registers are being programmed.

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