A.1. Signal descriptions

The ETM11RV signals are described in Table A.1.

Table A.1. ETM11RV signals

Signal nameInput/outputDescription
ASICCTL[7:0]OutputContents of the ASIC control register.
CLKInputMain clock, identical to the processor clock.
DBGACKInputIndicates that the core is in debug state. This is connected to the core general purpose DBGACK output, so that it can be used to know when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main core/ETM interface.
DBGnTRSTInputReset for JTAG TAP controller.
DBGTCKENInputSynchronous enable for the JTAG interface.
DBGTDIInputTest data in. Must be connected to DBGTDI input to the core.
DBGTDOOutputTest data out. Must be multiplexed externally with DBGTDO from the core, controlled by DBGTDOSEL.
DBGTDOSELOutputSelects between core and ETM DBGTDO.
DBGTMSInputTest mode select. Must be connected to the DBGTMS input to the core.
ETMCPADDRESS[14:0]InputCoprocessor interface address. The relevant fields of the MRC or MCR instruction are encoded here as follows: Bits 14:12 <Opcode_1> Bits 11:8 <CRn> Bits 7:4 <CRm> Bit 3 = 0 cp14 Bit 3 = 1 cp15 Bits 2:0 <Opcode_2> For an ETM register access: Opcode_1 = 0 CRn = 0 CRm = Bits 3:0 of the register number CP14 or CP15 Opcode_2 = Bits 6:4 of the register number.
ETMCPCOMMITInputCoprocessor interface commit. If this is LOW two cycles after ETMCPEnable is asserted, the transfer is canceled and must not take any effect.
ETMCPENABLEInputCoprocessor interface enable. ETMCPWrite and ETMCPAddress are valid this cycle, and the remaining signals are valid two cycles later.
ETMCPRDATA[31:0]OutputCoprocessor interface read data.
ETMCPWDATA[31:0]InputCoprocessor interface write value.
ETMCPWRITEInputCoprocessor interface read or write (asserted for write).
ETMDA[31:3]InputAddress for data transfer
ETMDACTL[17:0]InputData address interface control signals.
ETMDBGRQOutputRequest from the ETM11RV for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.
ETMDD[63:0]InputContains the data value for a Load, Store, MRC, or MCR instruction.
ETMDDCTL[3:0]InputInstruction interface control signals.
ETMENOutputTrace port enabled. Must not be used to power down functionality required by the ETM unless it only relates to the trace port.
ETMIA[31:0]InputAddress for executed instruction.
ETMIACTL[17:0]InputInstruction interface control signals.
ETMIARET[31:0]InputAddress to return to if branch is incorrectly predicted.
ETMPADV[2:0]InputPipeline advance signals.
ETMPWRUPOutputIndicates that the ETM is in use. When LOW, logic supporting the ETM must be clock-gated to conserve power.
ETMWFIPENDINGInputIndicates that the ARM1136JF-S or ARM1136J-S core is about to go into Standby mode, and that the ETM must drain its FIFO.
EVNTBUS[19:0]InputGives the status of the performance monitoring events. Used as extended external inputs.
EXTIN[3:0]InputExternal input resources.
EXTOUT[1:0]OutputExternal outputs.
FIFOPEEK[8:0]OutputFor validation purposes only. Indicates when various events occur before being written to the FIFO.
MAXEXTIN[2:0]InputExternal inputs supported by the ASIC (maximum 4). This appears in the configuration code register.
MAXEXTOUT[1:0]InputExternal outputs supported by the ASIC (maximum 2). This appears in the configuration code register.
MAXPORTSIZE[3:0]InputMaximum port size supported. This appears in the system configuration register. You must set this bus to one of the following values: b0000 4-bit port b0001 8-bit port b0010 16-bit port b0011 24-bit port b0100 32-bit port.
MUXINSELInputEnable test wrapper for shared inputs.
MUXOUTSELInputEnable test wrapper for shared outputs.
nETMWFIREADYOutputIndicates that ETM11RV FIFO is empty and that ETM11RV can be put into Standby mode.
nPORESETInputReset for most registers. This is a power-on reset, and must not be asserted during normal core reset to enable tracing through reset.
PORTMODE[2:0]OutputCurrently requested port mode.
PORTSIZE[3:0]OutputCurrently requested port size
SCANMODEInputSelects scan test mode.
SEInputScan enable
TRACECLKOutputClock for TRACEDATA[31:0] and TRACECTL.Data is valid on both edges of this clock for maximum integrity.
TRACECTLOutputUsed by trace capture devices. This signal is valid for the same time as TRACEDATA.Trigger = TRACECTL & !TRACEDATA[0] TraceDisabled = TRACECTL & TRACEDATA[0].
TRACEDATA[31:0]Output32-bit trace port. Only data on this bus has to be captured.
TRACEREADYInputIf this signal is LOW, FIFO draining is not permitted this cycle and TRACEVALID, TRIGGER, TRACECTL and TRACEDATA must hold the same values next cycle. The behavior of TRACECLK is undefined if this input is used.
TRACEVALIDOutputTrace is valid on this CLK cycle.Equivalent to !TRACECTL | !TRACEDATA[0], but only asserted for one CLK cycle. This can therefore be used as a clock enable for TRACECTL and TRACEDATA.
TRIGGEROutputTrigger output this cycle.Equivalent to TRACECTL & !TRACEDATA[0].
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