ADDR[31:0] is the 32-bit address bus which specifies the address for the transfer. All addresses are byte addresses, so a burst of word accesses results in the address bus incrementing by four for each cycle.

The address bus provides 4GB of linear addressing space. When a word access is signaled, the memory system must ignore the bottom two bits, ADDR[1:0], and when a halfword access is signaled the memory system must ignore the bottom bit, ADDR[0].