ARM7TDMI-S Technical Reference ManualRevision: r4p3
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7.9. Store register

A store register has two cycles:

  1. During the first cycle, the ARM7TDMI-S core calculates the address to be stored.

  2. During the second cycle, the ARM7TDMI-S core performs the base modification, and writes the data to memory (if required).

The store register cycle timings are shown in Table 7.12, where:

s

Represents current mode-dependent value.

t

Is either 0, when the T bit is specified in the instruction (STRT) or c at all other times.

Table 7.12. Store register instruction cycle operations 

Cycle

Address

Size

Write

Data

TRANS[1:0]

Prot0

Prot1

1

pc+2i

w/h

0

(pc+2i)

N cycle

0

s

2

da

b/h/w

1

Rd

N cycle

1

t

pc+3i

-

-

-

-

-

-

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