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| Non-Confidential | |
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| Home > Instruction Cycle Timings > Load coprocessor register (from memory to coprocessor) |
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The LoaD Coprocessor (LDC)
operation transfers one or more words of data from memory to coprocessor
registers.
The coprocessor commits to the transfer only when it is ready to accept the data. The WRITE line is driven LOW during the transfer cycle. When CPB goes LOW, the ARM7TDMI-S core produces addresses, and expects the coprocessor to take the data at sequential cycle rates. The coprocessor is responsible for determining the number of words to be transferred. An interrupt can cause the ARM7TDMI-S core to abandon a busy-waiting coprocessor instruction (see Consequences of busy-waiting).
The first cycle (and any busy-wait cycles) generates the transfer address. The second cycle performs the write-back of the address base. The coprocessor indicates the last transfer cycle by driving CPA and CPB HIGH.
The load coprocessor register cycle timings are shown in Table 7.18.
Table 7.18. Load coprocessor register instruction cycle operations
Cycle | Address | Size | Write | Data | TRANS[1:0] | Prot0 | CPnI | CPA | CPB | |
|---|---|---|---|---|---|---|---|---|---|---|
1 register ready | 1 | pc+8 | w | 0 | (pc+8) | N cycle | 0 | 0 | 0 | 0 |
2 | da | w | 0 | (da) | N cycle | 1 | 1 | 1 | 1 | |
pc+12 | ||||||||||
1 register not ready | 1 | pc+8 | w | 0 | (pc+8) | I cycle | 0 | 0 | 0 | 1 |
2 | pc+8 | w | 0 | - | I cycle | 1 | 0 | 0 | 1 | |
• | pc+8 | w | 0 | - | I cycle | 1 | 0 | 0 | 1 | |
n | pc+8 | w | 0 | - | N cycle | 1 | 0 | 0 | 0 | |
n+1 | da | w | 0 | (da) | N cycle | 1 | 1 | 1 | 1 | |
pc+12 | ||||||||||
m registers (m>1) ready | 1 | pc+8 | w | 0 | (pc+8) | N cycle | 0 | 0 | 0 | 0 |
2 | da | w | 0 | (da) | S cycle | 1 | 1 | 0 | 0 | |
• | da++ | w | 0 | (da++) | S cycle | 1 | 1 | 0 | 0 | |
m | da++ | w | 0 | (da++) | S cycle | 1 | 1 | 0 | 0 | |
m+1 | da++ | w | 0 | (da++) | N cycle | 1 | 1 | 1 | 1 | |
pc+12 | ||||||||||
m registers (m>1) not ready | 1 | pc+8 | w | 0 | (pc+8) | I cycle | 0 | 0 | 0 | 1 |
2 | pc+8 | w | 0 | - | I cycle | 1 | 0 | 0 | 1 | |
• | pc+8 | w | 0 | - | I cycle | 1 | 0 | 0 | 1 | |
n | pc+8 | w | 0 | - | N cycle | 1 | 0 | 0 | 0 | |
n+1 | da | w | 0 | (da) | S cycle | 1 | 1 | 0 | 0 | |
• | da++ | 0 | (da++) | S cycle | 1 | 1 | 0 | 0 | ||
n+m | da++ | w | 0 | (da++) | S cycle | 1 | 1 | 0 | 0 | |
n+m+1 | da++ | w | 0 | (da++) | N cycle | 1 | 1 | 1 | 1 | |
pc+12 |
Coprocessor operations are available only in ARM state.
| Copyright © 2001 ARM Limited. All rights reserved. | ARM DDI 0234B |
| Non-Confidential | |
| PDF version | |
| Home > Instruction Cycle Timings > Load coprocessor register (from memory to coprocessor) |