ARM7TDMI-S Technical Reference Manual

Revision: r4p3

Table of Contents

About this document
Intended audience
Typographical conventions
Timing diagram conventions
Further reading
Feedback on this document
Feedback on the ARM7TDMI-S processor
1. Introduction
1.1. About the ARM7TDMI-S processor
1.1.1. The instruction pipeline
1.1.2. Memory access
1.1.3. Memory interface
1.2. ARM7TDMI-S architecture
1.2.1. Instruction compression
1.2.2. The Thumb instruction set
1.3. ARM7TDMI-S block, core and functional diagrams
1.4. ARM7TDMI-S instruction set summary
1.4.1. ARM instruction summary
1.4.2. Thumb instruction summary
1.5. Differences between Rev 3a and Rev 4
1.5.1. Addition of EmbeddedICE-RT logic
1.5.2. Improved Debug Communications Channel (DCC) bandwidth
1.5.3. Access to DCC through JTAG
1.5.4. TAP controller ID register
1.5.5. More efficient multiple transfers
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.3. Memory formats
2.3.1. Big-endian format
2.3.2. Little-endian format
2.4. Instruction length
2.5. Data types
2.6. Operating modes
2.7. Registers
2.7.1. The ARM state register set
2.7.2. The Thumb state register set
2.7.3. The relationship between ARM state and Thumb state registers
2.7.4. Accessing high registers in Thumb state
2.8. The program status registers
2.8.1. The condition code flags
2.8.2. The control bits
2.8.3. Reserved bits
2.9. Exceptions
2.9.1. Exception entry/exit summary
2.9.2. Entering an exception
2.9.3. Leaving an exception
2.9.4. Fast interrupt request
2.9.5. Interrupt request
2.9.6. Abort
2.9.7. Software interrupt instruction
2.9.8. Undefined instruction
2.9.9. Exception vectors
2.9.10. Exception priorities
2.10. Interrupt latencies
2.10.1. Maximum interrupt latencies
2.10.2. Minimum interrupt latencies
2.11. Reset
3. Memory Interface
3.1. About the memory interface
3.2. Bus interface signals
3.3. Bus cycle types
3.3.1. Nonsequential cycles
3.3.2. Sequential cycles
3.3.3. Internal cycles
3.3.4. Merged I-S cycles
3.3.5. Coprocessor register transfer cycles
3.4. Addressing signals
3.4.1. ADDR[31:0]
3.4.2. WRITE
3.4.3. SIZE[1:0]
3.4.4. PROT[1:0]
3.4.5. LOCK
3.4.6. CPTBIT
3.5. Data timed signals
3.5.1. WDATA[31:0]
3.5.2. RDATA[31:0]
3.5.3. ABORT
3.5.4. Byte and halfword accesses
3.6. Using CLKEN to control bus cycles
4. Coprocessor Interface
4.1. About coprocessors
4.1.1. Coprocessor availability
4.2. Coprocessor interface signals
4.3. Pipeline-following signals
4.4. Coprocessor interface handshaking
4.4.1. The coprocessor
4.4.2. The ARM7TDMI-S core
4.4.3. Coprocessor signaling
4.4.4. Consequences of busy-waiting
4.4.5. Coprocessor register transfer instructions
4.4.6. Coprocessor data operations
4.4.7. Coprocessor load and store operations
4.5. Connecting coprocessors
4.5.1. Connecting a single coprocessor
4.5.2. Connecting multiple coprocessors
4.6. Not using an external coprocessor
4.7. Undefined instructions
4.8. Privileged instructions
5. Debugging Your System
5.1. About debugging your system
5.1.1. A typical debug system
5.2. Controlling debugging
5.2.1. Debug modes
5.2.2. Examining system state during debugging
5.3. Entry into debug state
5.3.1. Entry into debug state on breakpoint
5.3.2. Entry into debug state on watchpoint
5.3.3. Entry into debug state on debug request
5.3.4. Action of the ARM7TDMI-S in debug state
5.3.5. Clocks
5.4. Debug interface
5.4.1. Debug interface signals
5.5. ARM7TDMI-S core clock domains
5.6. The EmbeddedICE-RT macrocell
5.7. Disabling EmbeddedICE-RT
5.8. EmbeddedICE-RT register map
5.9. Monitor mode debugging
5.9.1. Enabling monitor mode
5.9.2. Restrictions on monitor-mode debugging
5.10. The debug communications channel
5.10.1. DCC control register
5.10.2. Communications through the DCC
5.11. Scan chains and the JTAG interface
5.11.1. Scan chain implementation
5.11.2. Controlling the JTAG interface
5.12. The TAP controller
5.12.1. Resetting the TAP controller
5.13. Public JTAG instructions
5.13.1. SCAN_N (0010)
5.13.2. INTEST (1100)
5.13.3. IDCODE (1110)
5.13.4. BYPASS (1111)
5.13.5. RESTART (0100)
5.14. Test data registers
5.14.1. Bypass register
5.14.2. ARM7TDMI-S device identification (ID) code register
5.14.3. Instruction register
5.14.4. Scan path select register
5.14.5. Scan chains 1 and 2
5.15. Scan timing
5.15.1. Scan chain 1 cells
5.16. Examining the core and the system in debug state
5.16.1. Determining the core state
5.16.2. Determining system state
5.17. Exit from debug state
5.18. The program counter during debug
5.18.1. Breakpoints
5.18.2. Watchpoints
5.18.3. Watchpoint with another exception
5.18.4. Debug request
5.18.5. System speed access
5.18.6. Summary of return address calculations
5.19. Priorities and exceptions
5.19.1. Breakpoint with Prefetch Abort
5.19.2. Interrupts
5.19.3. Data Aborts
5.20. Watchpoint unit registers
5.20.1. Programming and reading watchpoint registers
5.20.2. Using the data, and address mask registers
5.20.3. The control registers
5.21. Programming breakpoints
5.21.1. Hardware breakpoints
5.21.2. Software breakpoints
5.22. Programming watchpoints
5.23. Abort status register
5.24. Debug control register
5.24.1. Disabling interrupts
5.24.2. Forcing DBGRQ
5.24.3. Forcing DBGACK
5.25. Debug status register
5.26. Coupling breakpoints and watchpoints
5.26.1. Breakpoint and watchpoint coupling example
5.26.2. DBGRNG signal
5.27. EmbeddedICE-RT timing
6. ETM Interface
6.1. About the ETM interface
6.2. Enabling and disabling the ETM7 interface
6.3. ETM7 to ARM7TDMI-S (Rev 4) connections
6.4. Clocks and resets
6.5. Debug request wiring
7. Instruction Cycle Timings
7.1. About the instruction cycle timings
7.2. Instruction cycle count summary
7.3. Branch and ARM branch with link
7.4. Thumb branch with link
7.5. Branch and exchange
7.6. Data operations
7.7. Multiply, and multiply accumulate
7.8. Load register
7.9. Store register
7.10. Load multiple registers
7.11. Store multiple registers
7.12. Data swap
7.13. Software interrupt, and exception entry
7.14. Coprocessor data processing operation
7.15. Load coprocessor register (from memory to coprocessor)
7.16. Store coprocessor register (from coprocessor to memory)
7.17. Coprocessor register transfer (move from coprocessor to ARM register)
7.18. Coprocessor register transfer (move from ARM register to coprocessor)
7.19. Undefined instructions and coprocessor absent
7.20. Unexecuted instructions
8. AC Parameters
8.1. Timing diagrams
8.1.1. Timing parameters for data accesses
8.1.2. Coprocessor timing
8.1.3. Exception and configuration input timing
8.1.4. Debug timing
8.1.5. Scan timing
8.2. AC timing parameter definitions
A. Signal Descriptions
A.1. Signal descriptions
B. Differences Between the ARM7TDMI-S and the ARM7TDMI
B.1. Interface signals
B.2. ATPG scan interface
B.3. Timing parameters
B.4. ARM7TDMI-S design considerations
B.4.1. Master clock
B.4.2. JTAG interface timing
B.4.3. TAP controller
B.4.4. Interrupt timing
B.4.5. Address-class signal timing
B.4.6. ARM7TDMI signals not implemented on ARM7TDMI-S processor

List of Figures

1. Key to timing diagram conventions
1.1. The instruction pipeline
1.2. ARM7TDMI-S block diagram
1.3. ARM7TDMI-S core
1.4. ARM7TDMI-S functional diagram
2.1. Big-endian addresses of bytes within words
2.2. Little-endian addresses of bytes within words
2.3. Register organization in ARM state
2.4. Register organization in Thumb state
2.5. Mapping of Thumb state registers onto ARM state registers
2.6. Program status register format
3.1. Simple memory cycle
3.2. Nonsequential memory cycle
3.3. Back to back memory cycles
3.4. Sequential access cycles
3.5. Merged I-S cycle
3.6. Data replication
3.7. Use of CLKEN
4.1. Coprocessor busy-wait sequence
4.2. Coprocessor register transfer sequence
4.3. Coprocessor data operation sequence
4.4. Coprocessor load sequence
4.5. Coprocessor connections
5.1. Typical debug system
5.2. ARM7TDMI-S block diagram
5.3. Debug state entry
5.4. Clock synchronization
5.5. The ARM7TDMI-S core, TAP controller, and EmbeddedICE-RT macrocell
5.6. DCC control register
5.7. ARM7TDMI-S scan chain arrangements
5.8. Test access port controller state transitions
5.9. ID code register format
5.10. Scan timing
5.11. Debug exit sequence
5.12. EmbeddedICE-RT block diagram
5.13. Watchpoint control value, and mask format
5.14. Debug abort status register
5.15. Debug control register format
5.16. Debug status register format
5.17. Debug control and status register structure
8.1. Timing parameters for data accesses
8.2. Coprocessor timing
8.3. Exception and configuration input timing
8.4. Debug timing
8.5. Scan timing

List of Tables

1.1. Key to tables
1.2. ARM instruction summary
1.3. Addressing mode 2
1.4. Addressing mode 2 (privileged)
1.5. Addressing mode 3
1.6. Addressing mode 4 (load)
1.7. Addressing mode 4 (store)
1.8. Addressing mode 5
1.9. Operand 2
1.10. Fields
1.11. Condition fields
1.12. Thumb instruction summary
2.1. Register mode identifiers
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Exception vectors
3.1. Cycle types
3.2. Burst types
3.3. Transfer widths
3.4. PROT[1:0] encoding
3.5. Transfer size encoding
3.6. Significant address bits
3.7. Word accesses
3.8. Halfword accesses
3.9. Byte accesses
4.1. Coprocessor availability
4.2. Handshaking signals
4.3. Handshake signal connections
4.4. CPnTRANS signal meanings
5.1. Function and mapping of EmbeddedICE-RT registers
5.2. DCC control register bit assignments
5.3. Public instructions
5.4. Scan chain number allocation
5.5. Scan chain 1 cells
5.6. SIZE[1:0] signal encoding
5.7. Debug control register bit assignments
5.8. Interrupt signal control
6.1. ETM7 and ARM7TDMI-S (Rev 4) pin connections
7.1. Transaction types
7.2. Instruction cycle counts
7.3. Branch instruction cycle operations 
7.4. Thumb long branch with link 
7.5. Branch and exchange instruction cycle operations  
7.6. Data operation instruction cycle operations  
7.7. Multiply instruction cycle operations  
7.8. Multiply-accumulate instruction cycle operations 
7.9. Multiply long instruction cycle operations  
7.10. Multiply-accumulate long instruction cycle operations 
7.11. Load register instruction cycle operations 
7.12. Store register instruction cycle operations 
7.13. Load multiple registers instruction cycle operations
7.14. Store multiple registers instruction cycle operations   
7.15. Data swap instruction cycle operations 
7.16. Software interrupt instruction cycle operations  
7.17. Coprocessor data operation instruction cycle operations 
7.18. Load coprocessor register instruction cycle operations 
7.19. Store coprocessor register instruction cycle operations 
7.20. Coprocessor register transfer (MRC)  
7.21. Coprocessor register transfer (MCR)  
7.22. Undefined instruction cycle operations 
7.23. Unexecuted instruction cycle operations 
8.1. Provisional AC parameters
A.1. Signal descriptions
B.1. ARM7TDMI-S processor signals and ARM7TDMI hard macrocell equivalents
B.2. Unimplemented ARM7TDMI processor signals

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Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure 5.8 reprinted with permission IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary Scan Architecture Copyright 2001, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A28 September 2001First release of ARM7TDMI-S (Rev 4) processor
Revision B11 March 2004Second release
Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0234B