3.3.12. PrimeCell Identification Registers 0-3

The read-only SSMCPCellID0-3 Registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. You can treat the registers conceptually as a 32-bit register. The register acts as a standard cross-peripheral identification system. Figure 3.12 shows the bit assignment for the SSMCPCellID0-3 Registers.

Figure 3.12. PrimeCell identification Register bit assignments

The four 8-bit registers are described in the following subsections:

PrimeCell Identification Register 0

The read-only SSMCPCellID0 Register is hard-coded and the fields within the registers determine the reset value. Table 3.18 lists the bit assignment of the SMCPCellID0 Register.

Table 3.18. SMCPCellID0 Register bit assignments

Bits

Name

Function

[15:8]

-

Read undefined

[7:0]

SSMCPCellID0

These bits read back as 0x0D

PrimeCell Identification Register 1

The read-only SSMCPCellID1 Register is hard-coded and the fields within the registers determine the reset value. Table 3.19 lists the bit assignment of the SSMCPCellID1 Register.

Table 3.19. SSMCPCellID1 Register bit assignments

Bits

Name

Function

[15:8]

-

Read undefined

[7:0]

SSMCPCellID1

These bits read back as 0xF0

PrimeCell Identification Register 2

The read-only SSMCPCellID2 Register is hard-coded and the fields within the registers determine the reset value. Table 3.20 lists the bit assignment of the SMCPCellID2 Register.

Table 3.20. SMCPCellID2 Register bit assignments

Bits

Name

Function

[15:8]

-

Read undefined

[7:0]

SSMCPCellID2

These bits read back as 0x05

PrimeCell Identification Register 3

The read-only SSMCPCellID3 Register is hard-coded and the fields within the registers determine the reset value. Table 3.21 lists the bit assignment of the SSMCPCellID3 Register.

Table 3.21. SSMCPCellID3 Register bit assignments

Bits

Name

Function

[15:8]

-

Read undefined

[7:0]

SSMCPCellID3

These bits read back as 0xB1

Copyright © 2001-2005 ARM Limited. All rights reserved.ARM DDI 0236H
Non-Confidential