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| Home > Programmer’s Model > Register descriptions > PrimeCell Identification Registers 0-3 | |||
The read-only SSMCPCellID0-3 Registers are four 8-bit registers,
that span address locations 0xFF0-0xFFC. You
can treat the registers conceptually as a 32-bit register. The register acts
as a standard cross-peripheral identification system. Figure 3.12 shows the bit
assignment for the SSMCPCellID0-3 Registers.
The four 8-bit registers are described in the following subsections:
The read-only SSMCPCellID0 Register is hard-coded and the fields within the registers determine the reset value. Table 3.18 lists the bit assignment of the SMCPCellID0 Register.
The read-only SSMCPCellID1 Register is hard-coded and the fields within the registers determine the reset value. Table 3.19 lists the bit assignment of the SSMCPCellID1 Register.
The read-only SSMCPCellID2 Register is hard-coded and the fields within the registers determine the reset value. Table 3.20 lists the bit assignment of the SMCPCellID2 Register.
The read-only SSMCPCellID3 Register is hard-coded and the fields within the registers determine the reset value. Table 3.21 lists the bit assignment of the SSMCPCellID3 Register.