For memory banks constructed from 8-bit or non byte-partitioned memory devices, it is important that you clear the RBLE bit to zero within the respective Bank Control Register. This forces all nSMBLS[3:0] lines HIGH during a read access to that particular bank, because the byte lane selects are connected to the device write enables. Figure 2.31 shows 8-bit memory devices configuring memory banks that are 8, 16, and 32 bits wide. In each of these configurations, the nSMBLS[3:0] signals are connected to the write enable (nWE) inputs of each 8-bit memory.

For write transfers, the relevant nSMBLS[3:0] byte lane signals are asserted LOW, and steer the data to the addressed bytes.

For read transfers, all nSMBLS[3:0] lines are deasserted HIGH. This enables you to define the external bus for at least the width of the accessed memory.

For memory banks constructed from 16 or 32-bit memory devices, it is important that you set the RBLE bit to 1 within the respective Bank Control Register. This asserts all nSMBLS[3:0] lines LOW during a read access to that particular bank, because during a read, you must select all bytes of the devices to avoid un-driven byte lanes on the read data value.

For 16 and 32-bit wide memory devices, byte select signals exist and you must control these appropriately, as Figure 2.32 and Figure 2.33 show.

Figure 2.34 shows connections for a typical memory system with different data width memory devices.

The SSMC uses the programmed external memory width of each bank and the endianness to determine which remaining bytes it must drive to ensure that the external bus is never floating.

nSMDATAEN[3:0] controls the input/output pads cells for the external write data bus lines as Table 2.4 shows. Data is driven out on SMDATAOUT when nSMDATAEN is asserted LOW.

Table 2.5 to Table 2.10 list how the internal databuses HRDATASMC[31:0] and HWDATASMC[31:0] map onto the external databus. The two internal databuses are listed as HDATA[31:0] in the tables. This mapping of the data is affected by:

Table 2.5 to Table 2.10 lists how byte lane control and data bus steering is achieved for all combinations of:

For each access, the external bits on the SMDATA bus that map to the internal AHB bus HDATASMC are listed.

Table 2.5 lists the little-endian read accesses for an 8-bit external bus.

Table 2.6 lists the little-endian read accesses for a 16-bit external bus.

Table 2.7 lists the little-endian read accesses for a 32-bit external bus.

Table 2.8 lists the big-endian read accesses for an 8-bit external bus.

Table 2.9 lists the big-endian read accesses for a 16-bit external bus.

Table 2.10 lists the big-endian read accesses for a 32-bit external bus.