The SSMC is designed to enable an EBI to control the switching of the external data and address buses. For example, if you use the SSMC with an SDRAM controller that requires a bus multiplexor that can handle the necessary synchronization re-timing.

You must tie the SMEXTBUSMUX input HIGH to signal to use the EBI. This enables the external request and grant ports.

You must connect the SSMC and TIC bus request and grant ports to the EBI to ensure that, if you use the TIC, you connect it to the highest priority port because it must always be able to enter test mode. You must connect the SSMC address, data, and data enable to the relevant port on the EBI. You must also connect the SMBUSBACKOFFEBI signal to the EBI. The EBI uses this signal to tell the SSMC to release the external bus. There is no equivalent signal for the TIC because it is not necessary to release the bus when in test mode.

The handshaking between the EBI and the memory controller consists of a three-wire interface, EBIREQ, EBIGNT, and EBIBACKOFF, all active HIGH:

The EBI arbitration scheme keeps track of the memory controller that is currently granted and waits for the transaction from that memory controller to finish (EBIREQ taken LOW by the memory controller) before it grants the next memory controller. If a higher priority memory controller requests the bus then the EBIBACKOFF signal tells the currently granted memory controller to terminate the current transfer as soon as possible. Memory controller 1 has the highest priority and memory controller 3 the lowest priority.

When two memory controllers simultaneously request the EBI, the controller with the higher priority is granted use.

The EBI, as a peripheral, relies on the memory controllers to release their external requests for the external bus when they are idle, because it has no other knowledge of when a transfer starts or completes.

Figure 2.42 shows a simple handshake example. In this example, a device requests the external bus and is immediately granted because no other devices are requesting the bus.

If a higher priority device requests the bus, when a lower priority device is in control of the external bus then the EBIBACKOFF signal tells the lower priority device to release the bus as soon as possible. Figure 2.43 shows an example of this.

In Figure 2.43, a higher priority device requests the bus, shortly after a device has been granted the bus. The EBIBACKOFF signal tells the device to end the access early. Device 1 is granted the bus and completes its transfer. When the transfer is complete then device 2 is granted the bus and completes the transfer that was interrupted. The EBIREQ2 signal must be LOW for at least one clock cycle and after this, you can reassert it.