PrimeCell ™ SynchronousStatic Memory Controller (PL093) Technical Reference Manual

Revision: r0p4

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
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1. Introduction
1.1. About the SSMC
1.1.1. Features
1.1.2. Programmable parameters
1.2. Supported memory devices
1.2.1. Asynchronous memory devices
1.2.2. Synchronous memory devices
1.3. Product revisions
2. Functional Overview
2.1. About the SSMC
2.1.1. SSMC core
2.2. Operation
2.2.1. Clock frequency selection
2.2.2. Memory bank select
2.2.3. Access sequencing and memory width
2.2.4. Wait state generation
2.2.5. Write protection
2.2.6. Asynchronous static memory read control
2.2.7. Synchronous static memory read control
2.2.8. Asynchronous staticmemory write control
2.2.9. Synchronous staticmemory write control
2.2.10. Bus turnaround
2.2.11. Synchronous memory devices bus turnaround
2.2.12. Asynchronous external wait control
2.2.13. Synchronous external wait control
2.3. System-on-chip design considerations
2.3.2. Byte lane control
2.3.3. Clock feedback in SSMC
2.3.4. Example of system with single outputclock
2.4. Slave interface connection to theAHB
2.5. Memory shadowing
2.5.1. Booting from ROM after reset
2.5.2. External bank SMCS7 size configuration
2.6. Test interface controller
2.7. Using the SSMC with an EBI
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. Bank Idle Cycle Control Registers 0-7
3.3.2. Bank Read Wait State Control Registers 0-7
3.3.3. Bank Write Wait State Control Registers 0-7
3.3.4. Bank Output Enable Assertion DelayControl Registers 0-7
3.3.5. Bank Write Enable Assertion DelayControl Registers 0-7
3.3.6. Bank Control Registers 0-7
3.3.7. Bank Status Registers 0-7
3.3.8. Bank Burst Read Wait Delay ControlRegisters 0-7
3.3.9. SSMC Status Register
3.3.10. SSMC Control Register
3.3.11. Peripheral Identification Registers 0-3
3.3.12. PrimeCell Identification Registers 0-3
4. Programmer’s Model for Test
4.1. Scan testing
4.2. Test registers
4.2.1. SSMC Test Control Register
4.2.2. SSMC Test Output Register
4.2.3. SSMC Test Input Register
A. Signal Descriptions
A.1. AMBA AHB interface signals
A.2. AMBA AHB slave interface signals
A.3. AMBA AHB master interface signals
A.4. Non-AMBA signals
A.5. Input/output pad signals

List of Figures

1. Key to timing diagram conventions
1.1. Typical AHB-based microcontrollersystem
1.2. Typical AHB-based microcontrollersystem using an SDRAM controller
1.3. SSMC input and output connections
2.1. SSMC block diagram
2.2. SSMC core block diagram
2.3. External memory zero wait state read
2.4. External memory zero wait state readwith SMMEMCLK=HCLK/2
2.5. External memory zero wait state readwith SMMEMCLK=HCLK/3
2.6. External memory two wait state read
2.7. External memory two output enabledelay state read
2.8. Two zero wait state read transfers
2.9. External memory zero wait fixed lengthburst read
2.10. External burst ROM with WSTRD=2 andWSTBRD=1 fixed length burst read
2.11. External memory 32-bit burst readfrom 8-bit memory
2.12. External synchronous single transferread
2.13. External synchronous fixed lengthfour transfer burst read
2.14. External synchronous zero wait continuouslength burst read
2.15. External memory zero wait state read,WSTRD=3, WSTBRD=0, and SMMEMCLK=HCLK/2
2.16. External memory zero wait state write
2.17. External memory two wait state write
2.18. External memory two write enabledelay state write
2.19. External memory zero wait state write,bus not granted
2.20. External memory two zero wait writes
2.21. Synchronous two wait state write
2.22. Synchronous two wait state burstwrite with WSTWR=3 and WSTWEN=0
2.23. Read followed by write (WSTRD=WSTWR=0)with no turnaround (IDCY=0)
2.24. Write followed by read (WSTRD=WSTWR=0)with no turnaround (IDCY=0)
2.25. Read, then two writes (WSTRD=WSTWR=0),two turnaround cycles (IDCY=2)
2.26. External wait timed read transfer
2.27. External wait timed write transfer
2.28. External wait timed read transferwith external abort
2.29. Synchronous burst write, two-cycleexternal delay (WSTWR=2, WSTWEN=0)
2.30. External burst wait during synchronouscontinuous length burst read
2.31. Memory banks constructed from 8-bitmemory
2.32. Memory banks constructed from 16-bitmemory
2.33. Memory banks constructed from 32-bitmemory
2.34. Typical memory connection
2.35. Pad interface
2.36. Clock gating
2.37. 8-bit memory device interconnectionexample
2.38. 16-bit memory device interconnectionexample
2.39. 32-bit memory device interconnectionexample
2.40. Connection of SSMC to pad when usinga single clock
2.41. Example memory map
2.42. EBIREQ and EBIGNT signals when accessgranted immediately
2.43. Example use of EBIBACKOFF signal(EBICLK=MemCLK1=MemCLK2)
3.1. SMBIDCYRx Register bit assignments
3.2. SMBWSTRDRx Register bit assignments
3.3. SMBWSTWRRx Register bit assignments
3.4. SMBWSTOENRx Register bit assignments
3.5. SMBWSTWENRx Register bit assignments
3.6. SMBCRx Register bit assignments
3.7. SMBSRx Register bit assignments
3.8. SMBWSTBRDRx Register bit assignments
3.9. SSMCSR Register bit assignments
3.10. SSMCCR Register bit assignments
3.11. Peripheral identification Registerbit assignments
3.12. PrimeCell identification Registerbit assignments
4.1. SSMCITCR Register bit assignments
4.2. SSMCITOP Register bit assignments
4.3. SSMCITIP Register bit assignments

List of Tables

2.1. Static memory bank select coding
2.2. Address mapping for external memory banks
2.3. Address mapping for memory bank registers
2.4. SMDATAOUT controlled by nSMDATAEN
2.5. Little-endian read, 8-bit external bus
2.6. Little-endian read, 16-bit external bus
2.7. Little-endian read, 32-bit external bus
2.8. Big-endian read, 8-bit external bus
2.9. Big-endian read, 16-bit external bus
2.10. Big-endian read, 32-bit external bus
2.11. External size configuration values for bank 7
3.1. Register summary
3.2. SMBIDCYRx Register bit assignments
3.3. SMBWSTRDRx Register bit assignments
3.4. SMBWSTWRRx Register bit assignments
3.5. SMBWSTOENRx Register bit assignments
3.6. SMBWSTWENRx Register bit assignments
3.7. PrimeCell SSMC reset default memory width
3.8. SMBCRx Register bit assignments
3.9. SMBCRx example configurations
3.10. SMBSRx Register bit assignments
3.11. SMBWSTBRDRx Register bit assignments
3.12. SSMCSR Register bit assignments
3.13. SSMCCR Register bit assignments
3.14. SSMCPeriphID0 Register bit assignments
3.15. SSMCPeriphID1 Register bit assignments
3.16. SSMCPeriphID2 Register bit assignments
3.17. SSMCPeriphID3 Register bit assignments
3.18. SMCPCellID0 Register bit assignments
3.19. SSMCPCellID1 Register bit assignments
3.20. SMCPCellID2 Register bit assignments
3.21. SSMCPCellID3 Register bit assignments
4.1. SSMCITCR Register bit assignments
4.2. SSMCITOP Register bit assignments
4.3. SSMCITIP Register bit assignments
A.1. Common AMBA AHB signals
A.2. AMBA AHB slave interface signals
A.3. AMBA AHB slave memory interface signals
A.4. AMBA AHB master interface signals
A.5. Internal signal descriptions
A.6. Input/output pad signals


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 7December 2001 First release.
Revision B 14June 2002 Changes to signals and incorporationof errata.
Revision C 26March 2003 Update to r0p1 and incorporation oferrata.
Revision D 20August 2003 Update to include errata, corrections,and additions.
Revision E 27January 2004 Update to r0p2 and incorporation oferrata.
Revision F 07June 2004 Update to r0p3. Corrections and additionof note.
Revision G 06 October2004 Update to include errata and corrections.
Revision H 24January 2005 Update to r0p4 and incorporation oferrata.
Copyright © 2001-2005 ARM Limited. All rights reserved. ARM DDI 0236H