For correct test operation, you must instantiate the dedicated
test ports of the VFP9-S coprocessor as shown in Table 6.1.
Some of the signals are static and some are dynamic. During
a VFP9-S scan pattern, a dynamic input signal must get from
the chip port to the first flip-flop of a VFP9-S scan chain
within one test pattern cycle, depending on the setup-to-clock timing
in the pattern timeset. A dynamic output signal must get from the
last flip-flop to the port within one test cycle, depending on the
timing of the output valid strobe.
Table 6.1. VFP9-S test pins
| Pin | Direction | Type | Description |
|---|
| SCANMODE | Input | Static | Blocks output of reset synchronizer |
| DFTRESET | Input | Dynamic | Scan mode reset input |
| SE | Input | Dynamic | Scan enable for all internal clock domains
1 = shift 0 = no shift |
| SI | Input | Dynamic | Scan input port |
| SO | Output | Dynamic | Scan output port |
| DFTCKEN | Input | Static | Enables gating of VFP9-S clock |
| WSEI | Input | Dynamic | Scan enable for all dedicated input cells 1
= shift 0 = no shift |
| WSEO | Input | Dynamic | Scan enable for all dedicated output cells
1 = shift 0 = no shift |
| WSI | Input | Dynamic | Input ports for test wrapper scan chains |
| WSO | Output | Dynamic | Output ports for test wrapper scan chains |
| MUXINSEL | Input | Static | Configures dedicated input test wrapper cells
for functional mode or test mode |
| WEDGE | Input | Static | Selects clock edge that changes WSO 1 = rising edge 0 = falling edge |
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