The VFP9-S coprocessor handles exceptions imprecisely with respect to both the state of the ARM processor and the state of the VFP9-S coprocessor. It detects an exceptional instruction after the instruction passes the point for exception handling in the ARM processor. It then enters the exceptional state and signals the presence of an exception by refusing to accept a subsequent VFP instruction. The instruction that triggers exception handling bounces to the ARM processor. The bounced instruction is not necessarily the instruction immediately following the exceptional instruction. Depending on sequence of instructions that follow, the bounce can occur several instructions later.

The VFP9-S coprocessor can generate exceptions only on arithmetic operations and not on data transfer operations. Instructions that involve copying data between VFP9-S registers are nonarithmetic and cannot produce exceptions. These are FCPY, FABS, and FNEG. These instructions copy NaNs and subnormal operands without bouncing. NaNs retain all fraction bits regardless of the state of the DN bit, FPSCR[25]. SNaNs do not cause an Invalid Operation exception. Subnormal operands are not flushed to zero regardless of the state of the FZ bit, FPSCR[24].

In both Full-compliance and RunFast modes, the VFP9-S hardware, with support code, processes exceptions according to the IEEE 754 standard. VFP9-S exception processing includes calling user trap handlers with intermediate operands specified by the IEEE 754 standard.

For descriptions of each of the exception flags and their bounce characteristics, see the sections Invalid Operation exception to Arithmetic exceptions.