4.6.5. Double-precision source register locking
Table 4.3 shows
how the scoreboard locks source registers for double-precision instructions
in Full-compliance mode and in RunFast mode.
Table 4.3. Double-precision source register locking
| LEN | Vector length | Source registers
locked in Decode stage |
|---|
| Full-compliance mode | RunFast mode |
|---|
| 000 | 1 | Iteration 1 registers | - |
| 001 | 2 | Iterations 1-2 registers | - |
| 010 | 3 | Iterations 1-3 registers | Iteration 3 registers |
| 011 | 4 | Iterations 1-4 registers | Iteration 3-4 registers |
For example, the following double-precision, short vector
instruction has a vector length of four iterations (LEN = 011):
FADDD D4, D8, D12
In Full-compliance mode, the FADDD performs the following
operations:
FADDD D4, D8, D12 ; D8 and D12 locked in Decode stage
FADDD D5, D9, D13 ; D9 and D13 locked in Decode stage
FADDD D6, D10, D14 ; D10 and D14 locked in Decode stage
FADDD D7, D11, D15 ; D11 and D15 locked in Decode stage
In RunFast mode, the FADDD performs the following operations:
FADDD D4, D8, D12 ; No registers locked
FADDD D5, D9, D13 ; No registers locked
FADDD D6, D10, D14 ; D10 and D14 locked in Decode stage
FADDD D7, D11, D15 ; D11 and D15 locked in Decode stage
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