VFP9-S™ Vector Floating-point Coprocessor Technical Reference Manual

r0p2


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Typographical conventions
Further reading
ARM publications
Other publications
Feedback
Feedback on the VFP9-S coprocessor
Feedback on this manual
1. Introduction
1.1. About the VFP9-S coprocessor
1.2. Applications
1.3. Coprocessor interface
1.4. VFP9-S pipelines
1.4.1. The FMAC pipeline
1.4.2. FMAC pipeline execution
1.4.3. Divide and square root pipeline
1.4.4. Load and store pipeline
1.5. Modes of operation
1.5.1. Full-compliance mode
1.5.2. Flush-to-Zero mode
1.5.3. Default NaN mode
1.5.4. RunFast Mode
1.6. Short vector instructions
1.7. Using CPBURST
1.8. Parallel execution of instructions
1.9. VFP9-S treatment of branch instructions
1.10. Writing optimal VFP9-S code
1.11. Clocking
1.12. Testing
1.13. Silicon revision information
2. Register File
2.1. About the register file
2.2. Register file internal formats
2.2.1. Integer data format
2.2.2. Single-precision data format
2.2.3. Double-precision data format
2.3. Decoding the register file
2.4. Loading operands from ARM registers
2.5. Maintaining consistency in register precision
2.6. Data transfer between memory and VFP9-S registers
2.7. Access to register banks in CDP operations
2.7.1. About register banks
2.7.2. Operations using register banks
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Compliance with the IEEE 754 standard
3.2.1. An IEEE 754 standard-compliant implementation
3.2.2. Complete implementation of the IEEE 754 standard
3.2.3. IEEE 754 standard implementation choices
3.3. ARMv5TE coprocessor extensions
3.3.1. FMDRR
3.3.2. FMRRD
3.3.3. FMSRR
3.3.4. FMRRS
3.4. VFP9-S system control and status registers
3.4.1. Floating-point system ID register, FPSID
3.4.2. Floating-point status and control register, FPSCR
3.4.3. Floating-point exception register, FPEXC
3.4.4. Instruction registers, FPINST and FPINST2
4. Instruction Execution
4.1. About instruction execution
4.2. Serializing instructions
4.3. Interrupting the VFP9-S coprocessor
4.4. Forwarding
4.5. Hazards
4.6. Operation of the scoreboard
4.6.1. Full-compliance mode
4.6.2. RunFast mode
4.6.3. Single-precision source register locking
4.6.4. Single-precision source register clearing
4.6.5. Double-precision source register locking
4.6.6. Double-precision source register clearing
4.6.7. Data hazards in Full-compliance mode
4.6.8. Data hazards in RunFast mode
4.6.9. Resource hazards
4.7. Parallel execution
4.7.1. An example of parallel execution
4.8. Execution timing
5. Exception Handling
5.1. About exception processing
5.2. Support code
5.2.1. Bounced instructions
5.3. Illegal instructions
5.4. Determination of the trigger instruction
5.4.1. Exception processing for CDP scalar instructions
5.4.2. Exception processing for CDP short vector instructions
5.4.3. Examples of exception detection for short vector instructions
5.5. Input Subnormal exception
5.5.1. Exception enabled
5.5.2. Exception disabled
5.6. Invalid Operation exception
5.6.1. Exception enabled
5.6.2. Exception disabled
5.7. Division-by-Zero exception
5.7.1. Exception enabled
5.7.2. Exception disabled
5.8. Overflow exception
5.8.1. Exception enabled
5.8.2. Exception disabled
5.9. Underflow exception
5.9.1. Exception enabled
5.9.2. Exception disabled
5.10. Inexact exception
5.10.1. Exception enabled
5.10.2. Exception disabled
5.11. Input exceptions
5.12. Arithmetic exceptions
5.12.1. FADD/FSUB/FCMP/FCMPZ/FCMPE/FCMPEZ
5.12.2. FMUL/FNMUL
5.12.3. FMAC/FMSC/FNMAC/FNMSC
5.12.4. FDIV
5.12.5. FSQRT
5.12.6. FCPY/FABS/FNEG
5.12.7. FCVTDS/FCVTSD
5.12.8. FUITO/FSITO
5.12.9. FTOUI/FTOUIZ/FTOSI/FTOSIZ
6. Design for Test
6.1. VFP9-S coprocessor
6.1.1. Clock gating
6.1.2. Reset synchronizer
6.2. VFP9-S test wrapper
6.2.1. WSEI and WSEO
6.2.2. WEDGE
6.3. Test Pins
6.3.1. Test pin configuration in scan test with wrapper
6.3.2. Test pin configuration in functional mode
6.3.3. Test pin configuration in external test wrapper mode
7. Validating external connections
7.1. About using the test wrapper
7.2. Validation
A. Revisions
Glossary

List of Tables

2.1. VFP9-S MCR instructions
2.2. VFP9-S MRC instructions
2.3. VFP9-S MCRR instructions
2.4. VFP9-S MRRC instructions
2.5. Single­precision data memory images and byte addresses
2.6. Double­precision data memory images and byte addresses
2.7. Single‑precision three-operand register usage 
2.8. Single-precision two-operand register usage
2.9. Double-precision three-operand register usage
2.10. Double-precision two-operand register usage    
3.1. Default NaN values
3.2. Access to control registers
3.3. Encoding of the VFP9-S floating-point system ID register
3.4. Encoding of floating-point status and control register
3.5. Vector length and stride combinations
3.6. Encoding of the floating-point exception register
4.1. Single-precision source register locking
4.2. Single-precision source register clearing
4.3. Double-precision source register locking
4.4. Double-precision source register clearing for one-cycle instructions
4.5. Double-precision source register clearing for two-cycle instructions
4.6. Pipeline stages for Example 4.5
4.7. Pipeline stages for Example 4.6
4.8. Pipeline stages for Example 4.7
4.9. Pipeline stages for first iteration of Example 4.8
4.10. Pipeline stages for Example 4.9
4.11. Pipeline stages for first iteration of Example 4.10
4.12. Pipeline stages for Example 4.11
4.13. Pipeline stages for Example 4.12
4.14. Pipeline stages for Example 4.13
4.15. Pipeline stages for Example 4.14
4.16. Pipeline stages for Example 4.15, cycles 1 to 15
4.17. Pipeline stages for Example 4.15, cycles 16 to 31
4.18. Pipeline stages for Example 4.16
4.19. Throughput and latency cycle counts for VFP9-S CDP instructions 
5.1. Pipeline stages for Example 5.1
5.2. Pipeline stages for Example 5.2
5.3. Pipeline stages for Example 5.3
5.4. Possible invalid Operation exceptions
5.5. Default results for invalid conversion inputs
5.6. Rounding mode overflow results
5.7. LSA and USA determination
5.8. FADD family bounce thresholds
5.9. FMUL family bounce thresholds
5.10. FDIV bounce thresholds
5.11. FCVTSD bounce thresholds 
5.12. Single-precision float-to-integer bounce thresholds and stored results
5.13. Double-precision float-to-integer bounce thresholds and stored results, for unsigned results 
5.14. Double-precision float-to-integer bounce thresholds and stored results, for signed results 
6.1. VFP9-S test pins
6.2. VFP9-S test pins during scan test
6.3. VFP9-S test pins in functional mode
6.4. VFP9-S test pins in external test wrapper mode
7.1. VFP9 test wrapper cell order
A.1. Differences between issue B and issue C

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Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Some material in this document is based on ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final (information on a developed product).

Revision History
Revision A10 April 2002First release
Revision B20 October 2003First release for r0p2
Revision C04 August 2010Second release for r0p2
Copyright © 2002, 2003, 2008, 2010 ARM Limited. All rights reserved.ARM DDI 0238C
Non-Confidential