ARM9E-S Core ™ TechnicalReference Manual

Revision: r2p1

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the ARM9E‑S core
1.1.1. The instruction pipelines
1.1.2. Memory access
1.1.3. Forwarding, interlocking, and data dependencies
1.2. ARM9E‑S architecture
1.2.1. Instruction compression
1.2.2. The Thumb instruction set
1.3. ARM9E-S block, core, and interfacediagrams
1.4. ARM9E-S instruction set summary
1.4.1. Extended ARM instruction set summary
1.4.2. Thumb instruction set summary
1.5. Silicon revision information
1.5.1. Changes between ARM9E-S Rev 1 and Rev 2
1.5.2. Changes between ARM9E-S r2p0 and r2p1
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Memory formats
2.3.1. Big-endian format
2.3.2. Little-endian format
2.4. Instruction length
2.5. Data types
2.6. Operating modes
2.7. Registers
2.7.1. The ARM state register set
2.7.2. The Thumb state register set
2.7.3. ARM state and Thumb state registers relationship
2.7.4. Accessing high registers in Thumbstate
2.8. The program status registers
2.8.1. The condition code flags
2.8.2. The Q flag
2.8.3. The control bits
2.8.4. Reserved bits
2.9. Exceptions
2.9.1. Exception entry and exit summary
2.9.2. Entering an ARM exception
2.9.3. Leaving an ARM exception
2.9.4. Reset
2.9.5. Fast interrupt request
2.9.6. Interrupt request
2.9.7. Aborts
2.9.8. Software interrupt instruction
2.9.9. Undefined instruction
2.9.10. Breakpoint instruction (BKPT)
2.9.11. Exception vectors
2.9.12. Exception priorities
3. Memory Interface
3.1. About the memory interface
3.2. Instruction interface
3.2.1. Instruction interface signals
3.3. Instruction interface addressing signals
3.3.1. IA[31:1]
3.3.2. ITBIT
3.3.3. InTRANS
3.3.4. InM[4:0]
3.4. Instruction interface data timed signals
3.4.1. INSTR[31:0]
3.4.2. IABORT
3.5. Endian effects for instruction fetches
3.6. Instruction interface cycle types
3.6.1. Instruction interface, nonsequentialcycles
3.6.2. Instruction interface, sequentialcycles
3.6.3. Instruction interface, internal cycles
3.6.4. Canceled memory cycles
3.7. Data interface
3.7.1. Data interface signals
3.8. Data interface addressing signals
3.8.1. DA[31:0]
3.8.2. DLOCK
3.8.3. DMAS[1:0]
3.8.4. DnM[4:0]
3.8.5. DnRW
3.8.6. DnSPEC
3.8.7. DnTRANS
3.9. Data interface data timed signals
3.9.1. DABORT
3.9.2. RDATA[31:0]
3.9.3. WDATA[31:0]
3.9.4. Byte and halfword accesses
3.10. Data interface cycle types
3.10.1. Data interface, nonsequential cycles
3.10.2. Data interface, sequential cycles
3.10.3. DBURST[3:0]
3.10.4. Data interface, internal cycles
3.10.5. Data interface, coprocessor register transfer cycles
3.10.6. Canceled memory accesses
3.11. Endian effects for data transfers
3.11.1. Writes
3.11.2. Reads
3.12. Use of CLKEN to control bus cycles
3.12.1. Withdrawal of memory requests in waitedcycles
4. Interrupts
4.1. About interrupts
4.2. Hardware interface
4.2.1. Generating an interrupt
4.2.2. Synchronization
4.2.3. Re-enabling interrupts after an interruptexception
4.2.4. Interrupt registers
4.3. Maximum interrupt latency
4.4. Minimum interrupt latency
5. Coprocessor Interface
5.1. About the coprocessor interface
5.1.1. Coprocessor pipeline operates in stepwith the ARM9E-S core
5.1.2. Coprocessor pipeline one cycle behindthe ARM9E-S core
5.2. LDC/STC
5.2.1. Coprocessor handshake encoding
5.3. MCR/MRC
5.5. Interlocked MCR
5.6. Interlocked MCRR
5.7. CDP
5.8. Privileged instructions
5.9. Busy-waiting and interrupts
5.10. Coprocessor 15 MCRs
5.11. Connecting coprocessors
5.11.1. Connecting a single coprocessor
5.11.2. Connecting multiple coprocessors
5.11.3. No external coprocessor
5.11.4. Undefined instructions
6. Device Reset
6.1. About device reset
6.2. Reset modes
6.2.1. Full system reset
6.2.2. Core reset
6.2.3. EmbeddedICE-RT reset
6.2.4. Normal operation
6.3. ARM9E-S core behavior on exit fromreset
7. Instruction Cycle Times
7.1. Instruction cycle count summary
7.2. Introduction to detailed instructioncycle timings
7.3. Branch and ARM branch with link
7.4. Thumb branch with link
7.5. Branch and exchange
7.6. Thumb Branch, Link, and Exchange <immediate>
7.7. Data operations
7.8. MRS operations
7.9. MSR operations
7.10. Multiply and multiply accumulate
7.10.1. Interlocks
7.11.1. Interlocks
7.12. Load register
7.12.1. Interlocks
7.13. Store register
7.14. Load multiple registers
7.14.1. Interlocks
7.15. Store multiple registers
7.16. Load double register
7.17. Store double register
7.18. Data swap
7.18.1. Interlocks
7.19. PLD
7.20. Software interrupt, undefined instruction,and exception entry
7.21. Coprocessor data processing operation
7.22. Load coprocessor register, from memory
7.23. Store coprocessor register, to memory
7.24. Coprocessor register transfer, toARM
7.25. Coprocessor register transfer, fromARM register
7.26. Double coprocessor register transfer,to ARM register
7.27. Double coprocessor register transfer,from ARM register
7.28. Coprocessor absent
7.29. Unexecuted instructions
8. Debug Interface and EmbeddedICE-RT
8.1. About the debug interface
8.1.1. Halt mode
8.1.2. Monitor mode
8.2. Debug systems
8.2.1. The debug host
8.2.2. The protocol converter
8.2.3. The ARM9E‑S core
8.3. About EmbeddedICE-RT
8.4. Disabling EmbeddedICE-RT
8.5. Debug interface signals
8.5.1. Entry into debug state on breakpoint
8.5.2. Breakpoints and exceptions
8.5.3. Watchpoints
8.5.4. Watchpoints and exceptions
8.5.5. Debug request
8.5.6. Actions of the ARM9E‑S core in debug state
8.6. ARM9E‑S core clock domains
8.6.1. Clocks and synchronization
8.7. Determining the core and system state
8.8. The debug communications channel
8.8.1. Debug comms channel registers
8.8.2. Debug comms channel control register
8.8.3. Comms channel monitor mode debug statusregister
8.8.4. Communications using the comms channel
8.8.5. Comms channel reset
8.9. Monitor mode debug
8.10. Using watchpoints and breakpoints
8.10.1. Watchpoints
8.10.2. Breakpoints
8.10.3. Monitor mode
9. AC Parameters
9.1. Timing diagrams
9.2. AC timing parameter definitions
A. Signal Descriptions
A.1. Clock interface signals
A.2. Instruction memory interface signals
A.3. Data memory interface signals
A.4. Miscellaneous signals
A.5. Coprocessor interface signals
A.6. Debug signals
B. Debug in depth
B.1. Scan chains and JTAG interface
B.1.1. Debug scan chains
B.1.2. TAP state machine
B.2. Resetting the TAP controller
B.3. Instruction register
B.4. Public instructions
B.4.1. EXTEST (b0000)
B.4.2. SAMPLE/PRELOAD (b0011)
B.4.3. SCAN_N (b0010)
B.4.4. INTEST (b1100)
B.4.5. IDCODE (b1110)
B.4.6. BYPASS (b1111)
B.4.7. RESTART (b0100)
B.5. Test data registers
B.5.1. Bypass register
B.5.2. ARM9E-S core device identification(ID) code register
B.5.3. Instruction register
B.5.4. Scan path select register
B.5.5. Scan chains 1 and 2
B.6. ARM9E-S core clock domains
B.7. Determining the core and system state
B.7.1. Determining the core state
B.7.2. Determining the system state
B.7.3. Exit from debug state
B.8. Behavior of the program counter duringdebug
B.8.1. ARM and Thumb state breakpoints
B.8.2. ARM and Thumb state watchpoints
B.8.3. Watchpoint with another exception
B.8.4. Watchpoint and breakpoint
B.8.5. Debug request
B.8.6. System speed access
B.8.7. Summary of return address calculations
B.9. Priorities and exceptions
B.9.1. Breakpoint with Prefetch Abort
B.9.2. Interrupts
B.9.3. Data Aborts
B.10. EmbeddedICE-RT logic
B.10.1. Register map
B.10.2. Programming and reading EmbeddedICE-RT logic registers
B.10.3. Using the mask registers
B.10.4. Watchpoint control registers
B.10.5. Debug control register
B.10.6. Debug status register
B.10.7. Vector catch register
B.11. Vector catching
B.12. Coupling breakpoints and watchpoints
B.12.1. Breakpoint and watchpoint coupling example
B.12.2. DBGRNG signal
B.13. Disabling EmbeddedICE-RT
B.14. EmbeddedICE-RT timing

List of Figures

1. Key to timing diagram conventions
1.1. Five-stage pipeline
1.2. Typical pipeline sequence
1.3. ARM9E-S r2p1 core
1.4. ARM9E-S interfacediagram
1.5. ARM9E-S EmbeddedICE-RTlogic
2.1. Big-endian addresses of bytes withinwords
2.2. Little-endian addresses of byteswithin words
2.3. Register organizationin ARM state
2.4. Register organization in Thumb state
2.5. ARM state and Thumb state registersrelationship
2.6. Program status register
3.1. Simple memory cycle
3.2. Nonsequentialinstruction fetch cycle
3.3. Sequential instructionfetch cycles
3.4. Completed instruction fetch
3.5. Instruction Fetch canceled by IKILL
3.6. Canceled instruction fetch followedby a sequential access
3.7. Canceled instruction fetch followedby an internal cycle
3.8. Canceled instruction fetch followedby a nonsequential fetch
3.9. Two canceled sequential instructionfetches
3.10. ARM9E-S aborteddata memory access
3.11. Data replication
3.12. Simple memorycycle
3.13. Nonsequential data memory cycle
3.14. Back to back memorycycles
3.15. Sequential accesscycles
3.16. Completed data transfer
3.17. Data transfer canceled by DKILL
3.18. Back to back data transfer with DABORT
3.19. Use of CLKEN
3.20. Alteration of next memory requestduring waited bus cycle
4.1. Retaking the FIQ exception
4.2. Stopping CLK for power saving
4.3. Using CLK and CLKEN for best interruptlatency
5.1. ARM9E-S core LDC/STC cycle timing
5.2. ARM9E-S coprocessor clocking
5.3. ARM9E-S core MCR or MRC transfer timing
5.4. ARM9E-S core MCRR or MRRC transfertiming
5.5. ARM9E-S core interlocked MCR
5.6. ARM9E-S core interlocked MCRR
5.7. ARM9E-S core late-canceled CDP
5.8. ARM9E-S core privileged instructions
5.9. ARM9E-S core busy waiting and interrupts
5.10. ARM9E-S core coprocessor 15 MCRs
5.11. Coprocessor connections
6.1. System reset
6.2. ARM9E-S core behavioron exit from reset
8.1. Typical debug system
8.2. ARM9E-S core debug block diagram
8.3. The ARM9E‑S, TAP controller, and EmbeddedICE-RT
8.4. Breakpoint timing
8.5. Watchpoint entry with data processinginstruction
8.6. Watchpoint entry with branch
8.7. Clock synchronization
8.8. Debug comms channel control register
8.9. Coprocessor 14 monitor mode debugstatus register format
9.1. Instruction memory interface timing,InMREQ and ISEQ
9.2. Data memory interface timing
9.3. Clock enable timing
9.4. Coprocessor interface timing
9.5. Exception and configuration timing
9.6. Debug interface timing
9.7. Interrupt sensitivity status timing
9.8. JTAG interface timing
9.9. DBGSDOUT to DBGTDO relationship
9.10. PADV timing
B.1. ARM9E-S core scan chain arrangements
B.2. Test access port controller statetransitions
B.3. ID code register format
B.4. Typical scan chain cell
B.5. Debug exit sequence
B.6. ARM9E-S core EmbeddedICE macrocelloverview
B.7. Watchpoint control register for datacomparison
B.8. Watchpoint control register for instructioncomparison
B.9. Debug control register format
B.10. Debug status register
B.11. Debug control and status registerstructure
B.12. Vector catch register

List of Tables

1.1. Key to instruction set tables
1.2. ARM instruction set summary
1.3. Addressing modes
1.4. Oprnd2
1.5. Fields
1.6. Condition fields
1.7. Thumb instruction set summary
2.1. Register mode identifiers
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Configuration of exception vector address locations
2.5. Exception vectors
3.1. InTRANS encoding
3.2. Significant address bits
3.3. Halfword accesses
3.4. Cycle types
3.5. Burst types
3.6. Transfer widths
3.7. DnTRANS encoding
3.8. Significant address bits
3.9. Word accesses
3.10. Halfword accesses
3.11. Byte accesses
3.12. Cycle types
3.13. Burst types
3.14. DBURST[3:0] encoding
5.1. Handshake signals
5.2. Handshake signal connections
6.1. Reset modes
7.1. Key to tables
7.2. ARM instruction cycle counts
7.3. Key to cycle timing tables
7.4. Branch and ARM branch with link cycle timings
7.5. Thumb branch with link cycle timing
7.6. Branch and exchange cycle timing
7.7. Thumb branch, link, and exchange cycle timing
7.8. Data operation cycle timing
7.9. MRS cycle timing
7.10. MSR cycle timing
7.11. MUL and MLA cycle timing
7.12. MULS and MLAS cycle timing
7.13. SMULL, UMULL, SMLAL, and UMLAL cycle timing
7.14. SMULLS, UMULLS, SMLALS, and UMLALS cycle timing
7.15. SMULxy, SMLAxy, SMULWy, and SMLAWy cycle timing
7.16. SMLALxy cycle timing
7.17. QADD, QDADD, QSUB, and QDSUB cycle timing
7.18. Load register operation cycle timing
7.19. Cycle timing for load operations resulting in interlocks
7.20. Example sequence LDRB, ADD, and ADD cycle timing
7.21. Example sequence LDRB and STMIA cycle timing
7.22. Store register operation cycle timing
7.23. LDM cycle timing
7.24. STM cycle timing
7.25. Data swap cycle timing
7.26. PLD operation cycle timing
7.27. Exception entry cycle timing
7.28. Coprocessor data operation cycle timing
7.29. Load coprocessor register cycle timing
7.30. Store coprocessor register cycle timing
7.31. MRC instruction cycle timing
7.32. MCR instruction cycle timing
7.33. MRRC instruction cycle timing
7.34. MCRR instruction cycle timing
7.35. Coprocessor absent instruction cycle timing
7.36. Unexecuted instruction cycle timing
8.1. Coprocessor 14 register map
9.1. Target AC timing parameters
A.1. Clock interface signals
A.2. Instruction memory interface signals
A.3. Data memory interface signals
A.4. Miscellaneous signals
A.5. Coprocessor interface signals
A.6. Debug signals
B.1. Public instructions
B.2. Scan chain number allocation
B.3. Scan chain 1 bit order
B.4. ARM9E-S core EmbeddedICE-RT logic register map
B.5. Watchpoint control register for data comparison functions 
B.6. Watchpoint control register for instruction comparison functions
B.7. Debug control register bit functions
B.8. Interrupt signal control
B.9. Debug status register bit functions
B.10. Method of entry

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Figure B.2 reprintedwith permission IEEE Std 1149.1-1990, IEEE Standard Test AccessPort and Boundary-Scan Architecture Copyright 2001, by IEEE. TheIEEE disclaims any responsibility or liability resulting from theplacement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 02May 2002 First release
Revision B 30July 2004 Second release for r2p1
Copyright ©  2001, 2002, 2004 ARM Limited. All rights reserved. ARM DDI 0240B