Embedded Trace Buffer Technical Reference Manual 4.3. IEEE1149.1 Interface

4.3. IEEE1149.1 Interface

The IEEE1149.1 interface signals are shown in Figure 4.3.

Figure 4.3. IEEE1149.1 interface signals

The timing requirements for the IEEE1149.1 interface trace data signals are listed in Table 4.3. All figures are expressed as percentages of the TCK period at maximum operating frequency.

Note

A 0% figure in Table 4.3 indicates the hold time to clock edge plus the maximum clock skew for internal clock buffering.

Table 4.3. IEEE1149.1 interface timing requirements

Parameter	Description	Max	Min
T_ovttrans	Rising TCK to TDO output valid	40%	-
T_ohttrans	TDO output hold time from TCK rising	-	>0%
T_isttrans	JTAG inputs setup to rising CLK	-	40%
T_ihttrans	JTAG inputs hold from rising HCLK	-	0%
T_isntrst	nTRST input setup to rising CLK	-	40%
T_ihntrst	nTRST input hold from rising HCLK	-	0%

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