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The interface to the trace RAM uses the signals listed in Table 2.8.
Table 2.8. Trace RAM interface signals
| Signal | Description |
|---|---|
| CLK | clock |
| A | a configurable width address bus |
| CE | an active high chip enable signal |
| WE | an active high write enable signal |
| Din[RAM_BIT_WIDTH-1:0] | RAM data input bus |
| Dout[RAM_BIT_WIDTH-1:0] | RAM data output bus |
The timing requirements for the ETB are described in Chapter 4 Timing Requirements.
| Copyright © 2001-2002 ARM Limited. All rights reserved. | ARM DDI 0242B |
| Non-Confidential | |
| PDF version | |
| Home > Functional Description > Trace RAM interface > Signals |