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ATPG testing can only test out the interface between the ETB RAM and the ETB. It is unable to find faults in the actual RAM. A Built-In Self Test (BIST) interface is required that fully tests the RAM.
A block diagram of the BIST interface is shown in Figure 2.8.
The BISTEN signal gives an external BIST controller access to the inputs and outputs of the ETB RAM.It is not possible for the ETB to operate in functional mode when the BIST is testing the RAM. When BISTEN is HIGH do not:
set the TraceCaptEn bit.
write to the ETB RAM
read from the ETB RAM.
| Copyright © 2001-2002 ARM Limited. All rights reserved. | ARM DDI 0242B |
| Non-Confidential | |
| PDF version | |
| Home > Functional Description > BIST interface |