The relationship between HReq and CReq, and CAck and HAck is the same as it is for a read transfer. However, HReq cannot go HIGH the cycle after HSEL goes HIGH, because the data to be written only appears on HWDATA on the next cycle. Therefore, HReq goes HIGH one cycle later to allow for the write data to be registered before starting the synchronization between HCLK and CLK if the SBYPASS signal is LOW.

When CReq goes HIGH, the data is already valid on HWriteData (the registered version of HWDATA), and the address is already valid on HADDRReg. The CS/WE/RegWrite signals that control write access of the ETB RAM and the ETB registers then go HIGH for one cycle after CReq goes HIGH to perform the write access. CAck then goes HIGH one cycle after CReq goes HIGH to indicate that the write data has been used in the CLK domain.

At the same time that HAck goes HIGH, HREADYMEM goes HIGH indicating to the AHB bus master that the data has been written to its destination.

HReq then goes LOW, indicating that the AHB transfer has finished. This, in turn, causes CAck to go LOW one cycle after CReq goes LOW.

Finally, HAck goes LOW, finishing the write cycle.

A software write cycle with CLK and HCLK asynchronous are shown in Figure 2.14.

Software write cycles with CLK and HCLK synchronous (the SBYPASS signal is HIGH) is shown in Figure 2.15.