This is a single bit register that can be selected as the path between TDI and TDO to allow the device to be bypassed during boundary-scan testing. When the BYPASS instruction is the current instruction in the instruction register, the SHIFT-DR state transfers serial data from TDI to TDO with a delay of one TCK cycle. A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state.

Scan chain 0 accesses a 40-bit register with the same structure as the ETM TAP controller shift register:

Registers are read or written under the control of bit 39 (the r/w bit) and the register access occurs when the TAP state machine passes through the Update-DR state. The registers are described in Chapter 3 Programmer’s Model.