Embedded Trace Buffer Technical Reference Manual

(Rev 0)


Table of Contents

Preface
About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
Feedback
Feedback on the ETB
Feedback on this document
1. Introduction
1.1. About the Embedded Trace Buffer
1.2. ETM versions and variants
2. Functional Description
2.1. Functional information
2.1.1. Interfaces
2.1.2. Global configurability
2.1.3. ETM version compatibility
2.2. Operation
2.3. Control logic
2.4. Data Formatter
2.4.1. ETM architecture versions
2.4.2. Packet width
2.5. Trigger delay counter
2.6. Address generation
2.6.1. Write address generation
2.6.2. Read address generation
2.7. BIST interface
2.8. TAP controller
2.8.1. Test data registers
2.8.2. Instruction register
2.9. Trace RAM interface
2.9.1. Signals
2.9.2. Read access
2.9.3. Write access
2.10. Clocks, transfers, and resets
2.10.1. Clocks
2.10.2. Read transfer
2.10.3. Write transfer
2.10.4. Resets
3. Programmer’s Model
3.1. About the programmer’s model
3.1.1. Register fields
3.1.2. Register map
3.2. Register descriptions
3.2.1. Identification, register 0
3.2.2. RAM depth, register 1
3.2.3. RAM width, register 2
3.2.4. Status, register 3
3.2.5. RAM data, register 4
3.2.6. RAM read pointer, register 5
3.2.7. RAM write pointer, register 6
3.2.8. Trigger counter, register 7
3.2.9. Control, register 8
3.3. Software access to the ETB using the AHB interface
3.3.1. Restrictions on use of the AHB interface
3.4. Potential limitations
4. Timing Requirements
4.1. AHB interface
4.2. CLK domain
4.3. IEEE1149.1 Interface
A. Signal Descriptions
A.1. Signal properties and requirements
A.2. Signal descriptions
B. Integrating the ETB
B.1. Connection guide
B.2. Integrating the ETB with an ETMv1 device
B.2.1. Normal mode
B.2.2. Demultiplexed mode
B.3. Integrating the ETB with an ETMv2 device
B.3.1. Normal mode
B.3.2. Demultiplexed mode
B.4. Integrating the ETB with a generic trace port interface device
B.5. Connecting the ETB in a 64-bit AHB system
Glossary

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A18 December 2001First release.
Revision B5 February 2002Changes to signal names and add integration chapter.
Copyright © 2001-2002 ARM Limited. All rights reserved.ARM DDI 0242B
Non-Confidential