3.8.5. Operation

The following sections describe the operation of the Bus Matrix:

Integrating the Bus Matrix

When integrating the Bus Matrix component:

  • The input ports, with signal suffix S, are AHB slave ports, and must be connected accordingly.

  • The output ports, with signal suffix M, are AHB slave gasket ports. That is, they are designed to be attached directly to an AHB slave port, that they mirror, and must not be treated as full AHB master ports.

  • If the output from a Bus Matrix must be used as a bus master on a further AHB layer, it is recommended that a component such as an AHB bridge, for example, the ADK Ahb2AhbPass component, is used.


When connecting to an output port on the Bus Matrix, the HSEL pin must be connected to the attached slave even if there is only one slave present. If this is not done, the slave might see spurious transfers under certain circumstances.

Locked sequences

The Bus Matrix is only designed to support locked sequences that target a single output port. Because of this, a snooping bus across all input ports is not required. This provides arbitration for locked transfers on all layers simultaneously. In addition, the Bus Matrix is not designed to cope with a SPLIT response to a locked transfer. If this occurs, the Bus Matrix correctly passes the SPLIT response back to the initiating master, but it might then enable another master, connected to a different input port, to access the output port targeted by the first master.

Full AHB and AHB-Lite

The Bus Matrix inherently supports both full AHB and AHB-Lite systems. However, you must take care with SPLIT responses. The Bus Matrix correctly passes back a SPLIT response, but then relies on an arbiter on the AHB layer connected to the relevant input port to ensure that the initiating master is degranted until unsplit by the slave.

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