3.8.8. Arbitration and locked transfers

This section describes arbitration and locked transfers.


The arbitration within the BusMatrix module determines the input port that has access to the shared slave and each shared slave has its own arbitration. Different arbitration schemes provide different system characteristics in terms of access latency and overall system performance.

The slave switch supports the following arbitration schemes:

Fixed arbitration

One port always has highest priority and the order of priority for all other ports is fixed.

A burst transfer can be broken up if a higher-priority master requests the same slave, except where the burst transfer is a locked transfer.

Fixed (burst) arbitration

This is similar to fixed arbitration but it does not break defined length burst transfers and it is default arbitration for the Bus Matrix.

Round robin arbitration

Arbitration is performed during every active clock cycle, indicated by HREADYM. Priority initially goes to the lowest-numbered requestor, that is input port 0. When multiple requests are active, priority goes to the next lowest-numbered requestor compared to the currently active one. Fixed-length bursts are not broken. The arbitration waits for the end of the burst before passing control to the next requestor, if there is one. INCR bursts are treated as four-beat bursts, to optimize memory accesses, with guard logic to ensure that a sequence of short INCR bursts does not freeze the arbitration scheme.

Locked transfers

Using a multi-layer AHB system requires certain restrictions to be placed on the use of locked transfers to prevent a system deadlock. It is required that a sequence of locked transfers is performed to the same slave within the system. Because the minimum address space that can be allocated to a single slave is 1KB, a bus master can ensure this restriction is met by ensuring that it does not perform a locked sequence of transfers over a 1KB boundary, ensuring that it never crosses an address decode boundary.

Therefore, if a bus master is to perform two locked transfer sequences to different address regions, the bus master must not start the second locked transfer sequence until the final data phase of the first locked transfer sequence has completed.

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