3.8.4. BusMatrix module

The BusMatrix module, BusMatrix, enables multiple AHB masters from different AHB buses to be connected to multiple AHB slaves on multiple AHB slave buses. It enables parallel access to a number of shared AHB slaves from a number of different AHB masters. The Bus Matrix determines the master that gains access to each slave, and routes the control signals and data signals between them. This block is required in multi-layer AHB systems.

Figure 3.8 shows a block diagram of the BusMatrix module.

Figure 3.8. BusMatrix module components

Figure 3.8 shows a BusMatrix module components block diagram for (m+1) input ports, (n+1) output ports, 64-bit routing data width, 32-bit routing address width and 32-bit user signals width.

The Bus Matrix signal names have suffixes for port and pin naming:

The Bus Matrix connects to the masters and slaves using this naming scheme, with an additional integer to identify the correct master and slave. For example, connect HWDATAS0[63:0] to the 64-bit AHB Master 0 write data port, and HWDATAM0[63:0] to the AHB Slave 0 write data port.


If the Bus Matrix is configured using AMBA Designer, the signal names get appended with their associated interface names as a suffix. So for consistency, it is recommended to name the slave interfaces with the letter S plus an identifying integer and the master interfaces with the letter M plus an identifying integer.

Copyright © 2003, 2007 ARM Limited. All rights reserved.ARM DDI 0243C