3.8.7. Block functionality

Functionality of the BusMatrix module is described in the following sections:

Input stage

The input stage provides the following functions:

  • It registers and holds an incoming transfer if the receiving slave is not able to accept the transfer immediately.

  • If the Bus Matrix switches between input ports while in the middle of an undefined length burst, the input stage modifies the HTRANS and HBURST signals for the interrupted input port, so that when it is reinstated, the remaining transfers in the burst meet the AHB specification.

Decode stage

The decode-stage generates the select signal for individual slaves. It also handles the multiplexing of response signals and read data. During the address phase of a transfer, the decoder asserts the slave-select signal for the appropriate output stage corresponding to the address of the transfer. In addition the decoder routes an Active signal from the output stage back to the input stage. This signal indicates to the input that its address is currently being driven onto the chosen slave. During the data phase of a transfer the decoder routes the response signals and Read data back to the input port.

Each slave port, connected to an AHB master, is associated with a separate decoder. This enables the AHB masters to have independent address maps, that is a shared slave does not require to appear in the same address location for all masters. This is typically useful for multi-processor systems.

Any gaps in the memory map are redirected to a default slave, which returns an OKAY or ERROR response depending upon the type of access. There is an instance of a default slave associated with each decoder.

The decoder stage also supports the system address Remap function. A 4-bit Remap control signal connects to the decoder. Remapping might be used to change the address of physical memory or a device after the application has started executing. This is typically done to permit RAM to replace ROM when the initialization has been completed.

In multi-layer AHB systems that have local slaves on some of the AHB layers, the address decoding is performed in two stages. The first address decoder selects between local slaves and the shared slaves available through the AHB BusMatrix module. To support this, the decode-stage within the BusMatrix includes an HSEL input that indicates if the address from an input port is destined for a shared slave.

Output stage

The output stage has the following functions:

  • selects the address and control signals from the input stages

  • selects the corresponding write data from the input stage

  • determines when to switch between input ports in the input stage.

The output stage only selects an input source when that input has a transfer in the holding register.

The output stage generates an active signal for each input port when the address from that input port is being driven onto the slave. This signal enables the input stage to determine when transfers from other masters must be held up because the slave is not currently available.

When a sequence of transfers to a shared slave has finished and there are no more transfers to the slave required by any of the input ports, the output stage switches the address and control signals to an idle state.

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