3.8.10. Signal descriptions

Table 3.8 lists the signal list for the Bus Matrix.

Table 3.8. Bus Matrix signals

Signal

Direction

Description

HCLK

Input

System bus clock. Logic is triggered on clock rising edge.

HRESETn

Input

Activate low asynchronous reset.

System address control

REMAP[3:0]

Input

System address remap control.

Interface to masters (AHB slave)

HADDRSx[N]

Input

N-bit address bus from AHB master. N can be in the range [31 to 63].

HBURSTSx[2:0]

Input

Burst size information.

HMASTERSx[3:0]

Input

Current active master.

HMASTLOCKSx

Input

Indicate the transfer on the master AHB is a locked transfer.

HPROTSx[3:0]

Input

Protection information.

HRDATASx[63:0 or 31:0]

Output

Read data to bus master. Width configurable to be either 64-bit or 32-bit wide.

HREADYOUTSx

Output

HREADY signal feedback to the master bus, indicating if the AHB BusMatrix module is ready for next operation.

HREADYSx

Input

HREADY signal on the master AHB bus, indicating start/ending of transfer.

HRESPSx[1:0]

Output

Response from AHB BusMatrix module to AHB master. Width depends on architecture choice.

HSELSx

Input

Active HIGH select signal to indicate shared slave connected to the AHB BusMatrix module is selected.

HSIZESx[2:0]

Input

Size of the data.

HWDATASx[63:0 or 31:0]

Input

Write data from AHB masters. Width configurable to be either 64-bit or 32-bit wide.

HWRITESx

Input

Indication of WRITE/READ operation.

Interface to slaves (AHB master)

HADDRMx[N]

Output

N-bit address bus for AHB slave. N can be in the range [31 to 63].

HBURSTMx[2:0]

Output

Burst size information.

HMASTERMx[3:0]

Output

Current active master.

HMASTLOCKMx

Output

Indicates the transfer on the slave AHB is a locked transfer.

HPROTMx[3:0]

Output

Protection information.

HRDATAMx[63:0 or 31:0]

Input

Data read back from AHB slave(s). Width configurable to be either 64-bit or 32-bit wide.

HREADYOUTMx

Input

HREADY from AHB slave or slave multiplexor.

HREADYMUXMx

Output

HREADY feed back to all slaves on slave AHB.

HRESPMx[2:0]

Input

HRESP from AHB slave or slave multiplexor. Width depends on architecture choice.

HSELMx

Output

Active HIGH select signal to indicate slave bus is accessed. You can use this signal to drive a single AHB slave directly, or drive a secondary AHB decoder if multiple AHB slaves are used.

HSIZEMx[2:0]

Output

Size of the data.

HWDATAMx[63:0 or 31:0]

Output

Write data to AHB slave(s). Width configurable to be either 64-bit or 32-bit wide.

HWRITEMx

Output

Indicates write/read operation.

User signals  
HAUSERSxInputAdditional sideband bus that has same the timing as the slave interface address payload signals.
HWUSERSxInputAdditional sideband bus that has the same timing as the slave interface write data payload signals.
HRUSERSxOutputAdditional sideband bus that has the same timing as the slave interface read data payload signals.
HAUSERMxOutputAdditional sideband bus that has the same timing as the master interface address payload signals.
HWUSERMxOutputAdditional sideband bus that has the same timing as the master interface write data payload signals.
HRUSERMxInputAdditional sideband bus that has the same timing as the master interface read data payload signals.

User signals

The Bus Matrix supports USER signals on master and slave interfaces. These signals are optional, and a value of zero on the user_signal_width parameter removes them from the generated Verilog. If the user_signal_width parameter or the --userwidth command line switch is set to a non-zero value, that value defines the width of those USER signals. The USER signals have the same timing as the payload signals for that channel. For example, the HAUSER signals have the same timing as the address payload signals.

The USER signals are:

  • HAUSER

  • HRUSER

  • HWUSER.

N-bit addressing

The Bus Matrix supports N-bit addressing, that is, you can configure the address bus to be in the range of 32 bits up to 64 bits. By default the address width is set to 32 bits, but you can change this by supplying the --addrwidth command line switch or by changing the routing_address_width global parameter in AMBA Designer. Setting the address width affects both the slave ports and master ports address buses.

Note

The presence of USER signals and the support of N-bit addressing enables the Bus Matrix to fully connect to the AXI High Performance Matrix. The bus matrix user signals are fully mapped to their AXI counterparts. This is typically useful in mixed protocol designs. See the PrimeCell High-Performance Matrix PL301 Technical Reference Manual for more information.

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