1.2.1. AMBA AHB signals

Table 1.1 lists the AMBA AHB signals used in the ADK.

Table 1.1. AMBA AHB signals

Signal

Direction

Description

Slave

Master

Arbiter

Decoder

HADDR[31:0]

Input

Output

-

Input

The 32-bit system address bus.

HBURST[2:0]

Input

Output

Input

-

These signals indicate if the transfer forms part of a burst. Four, eight, and sixteen beat bursts are supported and the burst can be either incrementing or wrapping.

HBUSREQx

-

Output

Input

-

A signal from bus master x to the bus arbiter to indicate that the bus master requires the bus. There is an HBUSREQ signal for each bus master in the system, up to a maximum of 16 bus masters.

HCLK

Input

Input

Input

-

This clock times all bus transfers.

HGRANTx

-

Input

Output

-

This signal indicates that the bus master is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADY is HIGH, so the master gets access to the bus when both HREADY and HGRANT are HIGH.

HLOCK

-

Output

Input

-

When HIGH, this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

HMASTER[3:0]

Input

-

Output

-

These signals from the arbiter indicate the bus master that is currently performing a transfer and is used by the slaves that support SPLIT transfers to determine the master that is attempting an access. The timing of HMASTER is aligned with the timing of the address and control signals.

HMASTLOCK

Input

-

Output

-

Indicates that the current master is performing a locked sequence of transfers. This signal has the same timing as the HMASTER signals.

HPROT[3:0]

Input

Output

-

-

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that requires some level of protection.

The signals indicate if the transfer is an opcode fetch or data access, as well as if the transfer is a privileged mode access or User mode access. For bus masters with a memory management unit these signals also indicate whether the current access is cacheable or bufferable.

HRDATA[31:0] or HRDATA[63:0]

Output

Input

-

-

The read data bus transfers data from bus slaves to the bus master during read operations. ARM recommends a minimum data bus width of 32 bits. However, you can easily extend this to enable higher bandwidth operation.

HREADY

HREADYOUT

Input Output

Input -

Input -

- -

When HIGH, the HREADY signal indicates that a transfer has finished on the bus. You can drive this signal LOW to extend a transfer.

HRESETn

Input

Input

Input

Input

The bus reset signal is active LOW. It resets the system and the bus.

HRESP[1:0]

Output

Input

Input

-

The transfer response provides additional information on the status of a transfer. Four different responses are provided, OKAY, ERROR, RETRY, and SPLIT.

HSEL

Input

-

-

Output

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus.

HSIZE[2:0]

Input

Output

-

-

These signals indicate the size of the transfer, typically byte (8-bit), halfword (16-bit), or word (32-bit). The protocol permits larger transfer sizes up to a maximum of 1024 bits.

HSPLIT[15:0]

Output

-

Input

-

A split-capable slave uses the 16-bit split bus to indicate to the arbiter the bus masters that can reattempt a split transaction. Each bit of this split bus corresponds to a single bus master.

HTRANS[1:0]

Input

Output

Input

-

This indicates the type of the current transfer. This can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HWDATA[31:0] or HWDATA[63:0]

Input

Output

-

-

The write data bus transfers data from the master to the bus slaves during write operations. ARM recommends a minimum data bus width of 32 bits. However, you can easily extend this to enable higher bandwidth operation.

HWRITE

Input

Output

-

-

When HIGH, this signal indicates a write transfer, and when LOW, a read transfer.

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