1.2.2. AMBA APB signals

Table 1.2 lists the AMBA APB signals used in the ADK.

Table 1.2. AMBA APB signals

Signal

Type

Direction from bridge

Description

PADDR[31:0]

Peripheral address bus

Output

This is the APB address bus, and can be up to 32 bits wide. Individual peripherals use this bus for decoding register accesses to the peripheral. The address becomes valid after the first rising edge of the clock at the start of the transfer. If there is a following APB transfer, the address changes to the new value. Otherwise it holds its current value until the start of the next APB transfer.

PCLK

Peripheral clock

Input

This clock times all bus transfers. All events occur on rising edges of this signal.

PENABLE

Peripheral enable

Output

This enable signal times all accesses on the peripheral bus. PENABLE goes HIGH on the second clock rising edge of the transfer, and LOW on the third (last) rising clock edge of the transfer.

PRDATA[31:0]

Peripheral read data bus

Input

The peripheral read data bus is driven by the selected peripheral bus slave during read cycles, when PWRITE is LOW.

PRESETn

Peripheral reset

Input

The bus reset signal is active LOW and resets the system.

PSELx

Peripheral slave select

Output

There is one of these signals for each APB peripheral present in the system. The signal indicates that the slave device is selected, and that a data transfer is required. It has the same timing as the peripheral address bus. It becomes HIGH at the same time as PADDR, but is set LOW at the end of the transfer.

PWDATA[31:0]

Peripheral write data bus

Output

The peripheral write data bus is continuously driven by this module, changing during write cycles, when PWRITE is HIGH.

PWRITE

Peripheral transfer direction

Output

This signal indicates a write to a peripheral when HIGH, and a read from a peripheral when LOW.

It has the same timing as the peripheral address bus.

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