6.1. Operation

The PrimeCell GPIO is an AMBA-compliant System-on-Chip (SoC) peripheral. It is an AMBA slave module that connects to the Advanced Peripheral Bus (APB) compliant with AMBA Specification (Rev 2.0) onwards.

The GPIO offers:

The direction registers for port A and port B are programmable. Additional test registers and modes are implemented for functional verification and manufacturing test.

All block registers are cleared during power-on reset, PRESETn LOW. This enables the input drivers for both ports A and B that default to inputs on reset.

For each port, there is a data register and a data direction register. On reads, the data register contains the current status of corresponding port pins, and whether they are configured as input or output. Writing to a data register only affects the pins that are configured as outputs.

Additional test registers and modes are implemented for functional verification and manufacturing test.

For full details of the features provided by the PrimeCell GPIO, see the General Purpose Input/Output (PL061) Technical Reference Manual.

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