2.2.1. AHB components

This section summarizes the AHB components. For more details see Chapter 3 AHB Components.

Reset controller

  • generates a system-wide reset from power-on reset and watchdog reset signals.

Arbiter

  • uses a simple priority algorithm to control the master that has access to the AHB bus

  • provides three masters plus dummy

  • arbitration scheme defined in a separate sub-block for easy modification and reuse.

Retry slave, 32 or 64-bit

  • a starting point for a typical AHB slave design

  • simple four-word register bank plus read-only registers providing arithmetic combinations of the writable registers

  • higher order address bits control the response

  • supports retry response and wait states.

Static memory interface

  • AHB access to the external RAM and ROM

  • intended as a simple example

  • replaceable with PrimeCell Static Memory Controller (SMC) (PL241).

Test interface controller

  • now included within the static memory interface

  • converts test vectors applied on the external pins of the device into valid AHB transfers on an internal bus

  • to be used to test relevant ARM processor cores.

Bus matrix

  • enables parallel access paths between multiple masters and slaves

  • improves overall systems bandwidth

  • gives increased system design flexibility.

AHB to APB bridge

  • provides a 16-slot interface between the high-performance pipelined AHB and the lower performance peripheral bus

  • supports AMBA 3 APB protocol.

Example bus master (32 or 64 bit)

  • a simple bus master that is intended to act as a reference framework for bus master development

  • demonstrates bus master activity by read-pause-write bursts

  • interfaces through the AHB-Lite to AHB wrapper

  • configurable address and pause length.

AHB to AHB bridges

  • provide an interface between two separate AHB buses, supporting various clocking schemes.

Interrupt controller

  • generates the two ARM interrupt signals from the multiple interrupt sources that can exist in a system

  • individual bit-level control of the masking of interrupts

  • interrupt driven or polled method of operation

  • pin compatible with the PrimeCell Vectored Interrupt Controller (VIC) (PL190)

  • can be daisy-chained with the PrimeCell VIC.

Downsizer

  • AHB Slave gasket enables connection of 32-bit slave to a 64-bit bus.

Funnel

  • interfaces 32-bit slaves to a 64-bit bus where accesses are word size or smaller.

Copyright © 2003, 2007 ARM Limited. All rights reserved.ARM DDI 0243C
Non-Confidential