3.2.2. Signal descriptions

Table 3.2 lists the non-AMBA signals used by the arbiter.

Table 3.2. Arbiter signals descriptions

SignalTypeDirectionDescription

HBUSREQMx

Bus request

Input

This signal indicates that the bus master is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADY is HIGH, so the master gets access to the bus when both HREADY and HGRANTMx are HIGH.

HGRANTMx

Bus grant

Output

Lock signal from the bus master.

HLOCKMx

Locked transfers

Input

Indicates the bus master that owns the current data phase. Used by MuxM2S to remove the requirement for sequential logic within that block.

HMASTER[3:0]Bus masterOutputHMASTER[3:0] indicates the master that controls the current address phase.
HMASTERD[3:0]

Bus master

Output

HMASTERD[3:0] indicates the master that controls the current data phase.

Note

For a description of the AMBA signals used by the arbiter, see AMBA signals.

Copyright © 2003, 2007 ARM Limited. All rights reserved.ARM DDI 0243C
Non-Confidential