4.4. Watchdog unit

The Watchdog module is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral developed, tested and licensed by ARM Limited. The Watchdog module is an AMBA slave module and connects to the Advanced Peripheral Bus (APB).

The Watchdog module is based around a 32-bit down counter that is initialized from the Reload Register, WdogLoad. The watchdog clock generates a regular interrupt, WDOGINT, depending on a programmed value. The counter decrements by one on each positive clock edge of WDOGCLK when the clock enable WDOGCLKEN is HIGH. The watchdog monitors the interrupt and asserts a reset WDOGRES signal, when the counter reaches zero, and the counter is stopped. On the next enabled WDOGCLK clock edge the counter is reloaded from the WdogLoad Register and the count down sequence continues. If the interrupt is not cleared by the time that the counter next reaches zero then the Watchdog module reasserts the reset signal. The Watchdog module is intended to be used to apply a reset to a system in the event of a software failure, providing a way of recovering from software crashes. You can enable or disable the watchdog unit as required. Figure 4.6 shows the watchdog block diagram.

Figure 4.6. Watchdog components

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