4.5. Dual input timer

The ARM Dual-Timer module is an AMBA compliant SoC peripheral developed, tested and licensed by ARM Limited. For more information, see the AMBA Specification (Rev 2.0).

The Dual Input Timers module, Timers is an AMBA slave module and connects to the APB. The Dual-Timer module consists of two programmable 32/16-bit down counters that can generate interrupts on reaching zero. A Timer module can be programmed for a 32-bit or 16-bit counter size and one of three timer modes using the Control Register. The operation of each Timer module is identical. It has one of three timer modes:

The Dual Input Timers module, Timers, provides access to two interrupt-generating, programmable 32-bit Free-Running decrementing Counters (FRCs). The FRCs operate from a common timer clock, TIMCLK with each FRC having its own clock enable input, TIMCLKEN1 and TIMCLKEN2. Each FRC also has a prescaler that can divide down the enabled TIMCLK rate by 1, 16, or 256. This enables the count rate for each FRC to be controlled independently using their individual clock enables and prescalers.

The system clock, PCLK, controls the programmable registers, and the second clock input drives the counter, enabling the counters to run from a much slower clock than the system clock. The two clocks must be synchronous while register accesses are performed. TIMCLK can be equal to or be a submultiple of the PCLK frequency. However, the positive edges of TIMCLK and PCLK must be synchronous and balanced.

Figure 4.15 shows a top-level block diagram of the timers.

Figure 4.15. Dual input timer components

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