3.7.1. SMI programmer’s model

Eight memory banks are supported, with a separate chip select output for each bank. The chip select lines SMCS[7:0] for all banks are configurable to be either active HIGH or active LOW (default). The memory bank selection is controlled by the AMBA AHB address lines HADDR[28:26], as shown in Table 3.3, where all SMCS are shown as active HIGH.

Table 3.3. Static memory bank select coding, Remap = 1

HADDR[28:26]

SMCS[7:0]

Memory bank (Remap 1)

Memory bank (Remap 0)

000

00000001

Bank 0

Bank 7

001

00000010

Bank 1

Bank 1

010

00000100

Bank 2

Bank 2

011

00001000

Bank 3

Bank 3

100

00010000

Bank 4

Bank 4

101

00100000

Bank 5

Bank 5

110

01000000

Bank 6

Bank 6

111

10000000

Bank 7

Bank 7

The base address of the external memory banks and the base address of the SMI memory bank registers are defined in the AMBA AHB address decoder that generates the AHB slave select signal HSELSMC.

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