3.7.4. Signal descriptions

Table 3.7 lists non-AMBA signals used by the SMI. A number of pins, although present, are not used on the SMI, but are reserved for backward compatibility.

Table 3.7. Signal descriptions

Signal

Type

Direction

Description

BIGENDIAN

Input

System

Reserved.

CANCELSMWAIT

Input

Input pad

Reserved.

EXTBUSMUX

Input

System

Reserved.

HADDRTIC[31:0]

Output

AMBA AHB slave

The 32-bit system address bus.

HBURSTTIC[2:0]

Output

AMBA AHB slave

Indicates if the transfer forms part of a burst. The TIC always performs incrementing bursts of unspecified length.

HBUSREQTIC

Output

AMBA AHB arbiter

A signal from the TIC to the bus arbiter to indicate that it requires the bus.

HGRANTTIC

Input

AMBA AHB arbiter

This signal indicates that the TIC is currently the highest priority master. Ownership of the address or control signals changes at the end of the transfer when HREADYIN is HIGH.

HLOCKTIC

Output

AMBA AHB arbiter

When HIGH, this signal indicates that the TIC requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

HPROTTIC[3:0]

Output

AMBA AHB slave

The protection control signals indicate if the transfer is an opcode fetch or data access, as well as if the transfer is a Supervisor mode access or User mode access. These signals can also indicate whether the current access is cacheable or unbufferable.

HRDATATIC[31:0]

Input

AMBA AHB slave

The read data bus transfers data from bus slaves to the bus master during test read operations.

HREADYINTIC

Input

Other AHB TIC slaves

Transfer completed input. Multiplexed HREADY input from all slaves on TIC AHB bus.

HRESPTIC[1:0]

Input

AMBA AHB slave

The transfer response provides additional information on the status of a transfer. The TIC supports both SPLIT and RETRY responses.

HSELREG

Input

AMBA AHB decoder

Reserved.

HSELSMC

Input

AMBA AHB decoder

Slave select signal for PrimeCell AHB SMI memory banks.

HSIZETIC[2:0]

Output

AMBA AHB slave

Transfer size signal. This signal indicates the size of the current transfer, and can be byte (8-bit), halfword (16-bit), or word (32-bit). The TIC does not support larger transfer sizes.

HTRANSTIC[1:0]

Output

AMBA AHB slave

Indicates the type of the current transfer, and can be NONSEQUENTIAL, SEQUENTIAL, or IDLE. The TIC does not use the BUSY transfer type.

HWDATATIC[31:0]

Output

AMBA AHB slave

The write data bus transfers data from the master to bus slaves during write operations. A minimum data bus width of 32 bits is recommended. However, you can easily extend this to enable higher bandwidth operation.

HWRITETIC

Output

AMBA AHB slave

Transfer direction signal. When HIGH, this signal indicates a write to the SMI and when LOW, a read from the SMI.

MCADDR[31:0]

Input

Additional memory controller

Reserved.

MCBUSGNT

Output

Additional memory controller

Reserved.

MCBUSREQ

Input

Additional memory controller

Reserved.

MCDATAEN[3:0]

Input

Additional memory controller

Reserved.

MCDATAOUT[31:0]

Input

Additional memory controller

Reserved.

nHCLK

Input

Clock control

Reserved.

nSMBLS[3:0]

Output

Output pad

Byte lane select signals, active LOW. The signals nSMBLS[3:0] select byte lanes [31:24], [23:16], [15:8], and [7:0] on the data bus.

nSMDATAEN[3:0]

Output

Output pad

Tristate input/output pad enable for the byte lanes of the external memory data bus SMDATA[31:0], active LOW. Enables the byte lanes [31:24], [23:16], [15:8], and [7:0] of the data bus independently.

nSMOEN

Output

Output pad

Output enable for external memory banks, active LOW.

nSMWEN

Output

Output pad

Reserved.

REMAP

Input

System

Indicates the state of the memory map:

0 = reset memory map (SMCS7 mapped to SMCS0)

1 = normal memory map.

SCANENABLE

Input

System

Dummy pin that is used as a dedicated scan enable input.

SCANINHCLK

Input

System

Dummy pin that is used as a dedicated HCLK scan chain input.

SCANINnHCLK

Input

System

Reserved.

SCANOUTHCLK

Output

System

Dummy pin that is used as a dedicated HCLK scan chain input.

SCANOUTnHCLK

Output

System

Reserved.

SMADDR[25:0]

Output

Output pad

External memory address bus, to external memory banks.

SMBUSGNTEBI

Input

External bus multiplexor

Reserved.

SMBUSREQEBI

Output

External bus multiplexor

Reserved.

SMCS[7:0]

Output

Output pad

Chip select for external memory banks 7 to 0. The default is active LOW.

SMDATAIN[31:0]

Input

Input pad

External input data bus used to read data from memory bank.

SMDATAOUT[31:0]

Input

Input pad

External output data used to write data from SMI to memory bank.

SMMWCS7[1:0]

Input

Input pad

Reserved.

SMWAIT

Input

Input pad

Reserved.

TBUSOUTEBI[31:0]

Output

External bus multiplexor

Reserved.

TESTACK

Output

Output pad

The test bus acknowledge signal gives external indication that the TIC is granted and also indicates when a test access is complete. When TESTACK is LOW, the current test vector must be extended until TESTACK becomes HIGH.

TESTREQA

Input

Input pad

This is the Test Bus Request A input signal and is required as a dedicated device pin.

During normal system operation, the TESTREQA signal requests entry into the test mode. During test TESTREQA, in combination with TESTREQB, indicates the type of test vector that is applied in the following cycle.

TESTREQB

Input

Input pad

During test this signal, in combination with TESTREQA, indicates the type of test vector that is to be applied in the following cycle.

TICBUSGNTEBI

Input

External bus multiplexor

Reserved.

TICBUSREQEBI

Output

External bus multiplexor

Reserved.

TICREADEBI

Output

External bus multiplexor

Reserved.

Note

For a description of the AMBA signals used by the SMI, see AMBA signals.

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