3.7.3. TIC programmer’s model

The TIC operates as a standard AHB bus master during system test when the external test pins show that the system is required to enter test mode. In this mode, the TIC requests control of the AHB and, when granted, uses the AHB to perform system tests.

Table 3.4 shows the operation of the external test pins to change the TIC mode from normal operation into test mode.

Table 3.4. Test control signals during normal operation

TESTREQA

TESTREQB

TESTACK

Description

0

-

0

Normal operation

1

-

0

Enter test mode request

-

-

1

Test mode entered

During system test the external test pins control the operation of the TIC. Table 3.5 shows the operation of these pins.

Table 3.5. Test control signals during test operation

TESTREQA

TESTREQB

TESTACK

Description

-

-

0

Current access incomplete

1

1

1

Address vector or

Control vector or

Turnaround vector

1

0

1

Write vector

0

1

1

Read vector

0

0

1

Exit test mode

On entry into test mode the TIC indicates that it has switched to the test clock input by asserting the TESTACK signal.

Test vector types

The following types of test vector are associated with the test interface:

Address vector

The address for all subsequent read and write transfers is sampled by the TIC.

Write vector

The TIC performs an AHB write cycle, using the write data currently driven onto the external data bus.

Read vector

The TIC performs an AHB read cycle, driving the read data onto the external data bus when it becomes valid.

Control vector

Internal TIC registers are set, that control the types of read and write transfers that are performed.

Turnaround vector

Used between a read cycle and a write cycle to avoid clashes on the external data bus.

The address, control, and turnaround vectors are all indicated by the same value on the TESTREQA and TESTREQB signals. You can use the following rules to determine the type of vector that is being applied:

  • a read vector, or burst of read vectors, is followed by two turnaround vectors

  • when a single address or control vector is applied it is an address vector

  • when multiple address or control vectors are applied, they are all address vectors apart from the last that is a control vector.

Control vectors

The control vector determines the types of transfer the TIC can perform, by setting the values of the HSIZETIC, HPROTTIC, and HLOCKTIC AHB master outputs.

The default TIC bus master transfer type is:

32-bit transfer width

HSIZETIC[2:0] signifies word transfer.

Privileged system access

HPROTTIC[3:0] signifies supervisor data access, uncacheable and unbufferable.

Bit 0 of the control vector indicates if the control vector is valid. Therefore, if a control vector is applied with bit 0 LOW, the vector is ignored and does not update the control information. This mechanism enables address vectors that have bit 0 LOW to be applied for many cycles without updating the control information.

Although the default settings are sufficient for testing many systems, you can use the control vectors to change the control signals of the transfer, and also to select whether the TIC must generate fixed addresses or incrementing addresses.

Table 3.6 defines the bit positions of the control vector. The control vector bit definitions are designed to be backwards compatible with earlier versions of the TIC and therefore not all of the control bits are in obvious positions.

Table 3.6. Control vector bit definitions

Bit position

Description

0

Control vector valid

1

Reserved

2

HSIZETIC[0]

3

HSIZETIC[1]

4

HLOCKTIC

5

HPROTTIC[0]

6

HPROTTIC[1]

7

Address increment enable

8

Reserved

9

HPROTTIC[2]

10

HPROTTIC[3]

There is no mechanism to control the types of burst that the TIC can perform and only incrementing bursts of an undefined length are supported. The TIC only supports 8-bit, 16-bit, and 32-bit transfers. Therefore, you cannot alter HSIZETIC[2] and it is always LOW.

To support burst accesses using the test interface, the TIC can support incrementing of the bus address. The TIC increments eight address bits and the address range that can be covered by this incrementer depends on the size of the transfers being performed.

The control vector can enable and disable the address incrementer within the TIC. This enables burst accesses to incremental addresses, as used for testing internal RAM. Alternatively, you can disable the address increment so that successive accesses of a burst occur to the same address, as required to continually read from a single peripheral register.

The address incrementer is disabled by default and you must enable it using a control vector before use.

Note

The control vector primarily changes signals that have the same timing as the address bus. However, it also enables you to change the lock signal, that is actually required before the locked transfer commences. If the HLOCKTIC signal is used during testing it must be set one cycle before the transfer in which it is required. This difference in timing on the HLOCKTIC signal can, in some cases, cause an additional transfer to be locked both before and after the sequence that must in fact be locked.

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