3.15. Interrupt controller

The interrupt controller, Interrupt, provides a software interface to the interrupt system. In an ARM system, two levels of interrupt are available:

Only a single FIQ source at a time is generally used in a system, to provide a true low-latency interrupt. This has the following benefits:

There are 32 interrupt lines. The interrupt controller uses a bit position for each different interrupt source. The software can control each request line to generate software interrupts.


Unused interrupt lines must be tied LOW to disable them.

Figure 3.33 shows a block diagram of the interrupt controller.

Figure 3.33. Interrupt controller components

The nonvectored and daisy-chained IRQ interrupts provide an address for an Interrupt Service Routine (ISR). Reading from the vector interrupt address register, ICVectAddr, provides the address of the ISR, and updates the interrupt priority hardware that masks out the current and any lower priority interrupt requests. Writing to the ICVectAddr register indicates to the interrupt priority hardware that the current interrupt is serviced, enabling lower priority interrupts to go active.

The FIQ interrupt has the highest priority, followed by nonvectored IRQ interrupts. Daisy-chained interrupts have the lowest priority. A programmed interrupt request enables you to generate an interrupt under software control. This register is typically used to downgrade an FIQ interrupt to an IRQ interrupt.


The priority of the FIQ over IRQ is set by the ARM core. The interrupt controller can raise both an FIQ and an IRQ at the same time.

The IRQ and FIQ request logic has an asynchronous path. This enables interrupts to be asserted when the clock is disabled.

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