| Copyright © 2003, 2007 ARM Limited. All rights reserved. | ARM DDI 0243C |
| Non-Confidential | |
 PDF version | |
| Home > AHB Components > Synchronous AHB to AHB bridge |
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The AHB-AHB bridges (Ahb2Ahb32, Ahb2Ahb64, Ahb2AhbPass32, Ahb2AhbPass64, Ahb2AhbSyncDn32, Ahb2AhbSyncDn64, Ahb2AhbSyncUp32,
and Ahb2AhbSyncUp64) provide a unidirectional
link between two AHB domains. They enable a master to access a slave on
another bus, with the transfer initiated from one side only. These
bridges enable various synchronous clocking schemes to be implemented
between the AHB buses. Each bridge is implemented with an AHB slave
interface and an AHB-Lite master interface. These are packaged with
an AHB-Lite to AHB master gasket if full AHB master support is required.
An asynchronous bridge is also available (see Asynchronous AHB-AHB bridge).
The synchronous bridges have the following features:
32 or 64-bit data bus
bursts are preserved across the bridge, although subject to override if the bridge master is degranted
transfer sequences can be locked across the bridge
SPLIT and RETRY responses are serviced by the bridge, so remain local to the issuing slave
fully registered designs, except for Ahb2AhbPass
in-burst pre-emptive address generation, to reduce latency on read transfers
read transfers incur a minimum of one wait state
buffered writes are zero wait-state minimum, nonbufferable writes incur a minimum of two wait-states
modular design to facilitate the removal of logic that is not essential for a particular application.
| Copyright © 2003, 2007 ARM Limited. All rights reserved. | ARM DDI 0243C |
| Non-Confidential | |
| PDF version | |
| Home > AHB Components > Synchronous AHB to AHB bridge |