3.2.1. Operation

Operation of the arbiter is described in the following sections:

Arbitration scheme

The arbiter contains a fixed arbitration scheme that supports connection of three AHB bus masters, plus the dummy master. The priority scheme is as follows:

  • HBUSREQ3 is the highest priority.

  • HBUSREQ0 is the second highest priority. This must only be connected to a Pause input because it requests that the dummy master is granted the bus.

  • HBUSREQ2 is the third highest priority.

  • HBUSREQ1 is the lowest priority and default bus master. This input is usually used for an uncached ARM core, for example ARM7TDMI.

The arbiter re-arbitrates on every rising edge of HCLK, and so can potentially degrant a master part way through a burst. However, if a master has already commenced a fixed-length burst (that is, HBURST is not SINGLE or INCR), the arbiter does not re-arbitrate until the fixed-length burst has completed.

Because the HBUSREQ/HGRANT logic is pipelined, if a higher priority master requests the bus in the cycle before the current master begins a fixed-length burst, the current master performs the first access in the fixed length burst and is then degranted. You can change this behavior, but only by introducing a combinatorial path from HTRANS or HBURST to HGRANT within the arbiter. This would fail to meet the required timing budget.

Dummy master

Bus master 0 is reserved for the dummy bus master, that never performs real transfers. This master is granted in the following conditions:

  • when the previously granted master is performing a locked transfer that has received a SPLIT response

  • when the default master receives a SPLIT response and no other master is requesting the bus

  • when all masters have received SPLIT responses.


See the AMBA FAQ on the ARM Limited website for more details of the dummy master.


When a master declares a locked sequence of transfers (through HLOCK), the arbiter ensures that no other master is granted access to the bus until the first master completes the locked sequence. During the locked sequence, the arbiter asserts HMASTLOCK. If the master receives a SPLIT response to a locked transfer, the arbiter grants the dummy master until the first master is unsplit, indicated by the slave asserting the relevant bit of the HSPLIT bus. During this time, the arbiter deasserts the HMASTLOCK signal.


Further arbitration schemes within the bus hierarchy, such as within a multi-layer bus matrix, or within a multi-port slave, must also track the SPLIT/LOCK combination if this behavior is to be fully supported by a system.

To avoid system issues, ARM Limited recommends that masters never perform locked sequences to slave regions that can give a SPLIT response. SPLIT-capable slaves must respond with wait states to a locked transfer, rather than responding with SPLIT.

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